DDR linker script for Cortex-M4 on i.MX 8QuadMax using TCM for quick data/code access

[Cryptic]

The following snippet is taken from the MIMX8QM6xxxFF_cm4_core0_ddr_ram.ld template linker script in the SDK:

  __TDATA_ROM = __DATA_ROM + SIZEOF(.data); /* Symbol is used by startup for TCM data initialization */
  .quickaccess : AT(__TDATA_ROM)
  {
    __quickaccess_start__ = .;
    . = ALIGN(32);
    *(CodeQuickAccess)
    . += SAFE_BOUNDARY_LEN;
    *(DataQuickAccess)
    . = ALIGN(128);
    __quickaccess_end__ = .;
  } > m_tcml

Few questions:

• Why are the CodeQuickAccess 32-byte, and DataQuickAccess 128-byte aligned? Why can't we live with 4-byte alignment?
• Is it possible to break the .quickaccess section into two parts, such that we entirely dedicate m_tcml to CodeQuickAccess and m_tcmu to DataQuickAccess?

Here's the memory specification overview:

MEMORY
{
  m_interrupts          (RX)  : ORIGIN = 0x88800000, LENGTH = 0x00000A00
  m_text                (RX)  : ORIGIN = 0x88800A00, LENGTH = 0x003FF600
  m_data                (RW)  : ORIGIN = 0x88C00000, LENGTH = 0x00400000
  m_data2               (RW)  : ORIGIN = 0x89000000, LENGTH = 0x07000000
  m_tcml                (RW)  : ORIGIN = 0x1FFE0020, LENGTH = 0x0001FFE0
  m_tcmu                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00020000
}

Thanks!

[Dhruvit]

Hi @Cryptic,

I hope you are doing well

• Why are the CodeQuickAccess 32-byte, and DataQuickAccess 128-byte aligned? Why can't we live with a 4-byte alignment?

=> Yes, We can use 4 byte alignment.

• Is it possible to break the .quickaccess section into two parts, such that we entirely dedicate m_tcml to CodeQuickAccess and m_tcmu to DataQuickAccess?

=> Yes, It is possible to do the same. But it is not recommended to change the linker script other than the default.

Thanks & Regards,

Dhruvit Vasavada