DDR Display clock for the parallel display interface ?

[SimonFrey]

Hello,

is there a way to generate a DDR pixel clock for the parallel display port? 

I need to connect a UXGA LCD Display which has an even and an odd LVDS inteface. Each running at 85MHz. So if i configure the DI to output data at 170MPixels/sec with a 85MHz  clock instead of 170MHz, i could latch the even pixels in a buffer at rising edge from this clock and send the buffered even pixel and the actual odd pixel at falling egde through LVDS transmitters.

So to summarize, is there a way to change the SDR Display port clock to a DDR one for the same Pixel rate?

Thank you in advance

Simon

[Yanfei_Sun]

Hi Simon,

please check my comments.

Best Regards,

Ray

Simon Frey said:

Hi Ray,

it's right. I want to connect on Dual LVDS RAM less lcd display with 1600*1400 resolution @ ~60Hz with MX53QSB. I can't use the LDB module of the board since only one LVDS channel is available. So I have to make an adapter board between the Parallel port (J13 on QSB Samtec connector) and the dual LVDS LCD interfaces.

So that is how it should work.

The QSB use DI0_PIN2 as HSYNC, DI0_PIN3 as VSYNC and DI0_PIN15 as DataReady. DI0_PIN1 is available as alternate mode on the J13 pin DISP0_SER_SCLK (this one should be my DDR clock). The DI0_PIN1 Waveform should always be rising for Even Pixels and falling for Odd Pixels.

What i found in the IPUv3 driver is that the PIN1 generate an internal vsync for anti tearing purpose (i think)... i could move it to an other wave (6 for example) but i don't know how and where is this signal used...

[Ray] it's for internal logic. you cannot move it to others, since waveform A can only refer to the wavefoms with smaller index. that means wave3(for vsync) can not refer to wave6 as you expect.

For the second part, i saw in the iMX53 Reference Manual (rev2) that the DI0 Clock can be set from 20 to 170MHz (page 555). And i found a register IPU_PM (Power Modes Control Register page 2962). A could set the period to 170Mhz/1.125 = 151.11MHz :). I have to try.

Next question...

I'm actualy using the linaro ubuntu kernel BSP.. But i finally want to use Android ICS. are the IPU drivers the same ?? is it the same kernel architectur?

[Ray] yes they should be the same.

Thank

Simon

[SimonFrey]

Hi Ray,

it's right. I want to connect on Dual LVDS RAM less lcd display with 1600*1400 resolution @ ~60Hz with MX53QSB. I can't use the LDB module of the board since only one LVDS channel is available. So I have to make an adapter board between the Parallel port (J13 on QSB Samtec connector) and the dual LVDS LCD interfaces.

So that is how it should work.

The QSB use DI0_PIN2 as HSYNC, DI0_PIN3 as VSYNC and DI0_PIN15 as DataReady. DI0_PIN1 is available as alternate mode on the J13 pin DISP0_SER_SCLK (this one should be my DDR clock). The DI0_PIN1 Waveform should always be rising for Even Pixels and falling for Odd Pixels.

What i found in the IPUv3 driver is that the PIN1 generate an internal vsync for anti tearing purpose (i think)... i could move it to an other wave (6 for example) but i don't know how and where is this signal used...

For the second part, i saw in the iMX53 Reference Manual (rev2) that the DI0 Clock can be set from 20 to 170MHz (page 555). And i found a register IPU_PM (Power Modes Control Register page 2962). A could set the period to 170Mhz/1.125 = 151.11MHz :). I have to try.

Next question...

I'm actualy using the linaro ubuntu kernel BSP.. But i finally want to use Android ICS. are the IPU drivers the same ?? is it the same kernel architectur?

Thank

Simon

[Yanfei_Sun]

Hi Simon,

I'm assuming you are talking about LVDS display in split mode on the MX53QSB board.

for question 1:

you are using a sync panel, right? the IPU would output the parallel data together with HSYNC/VSYNC/DE, then converted to LVDS in LDB module. and DI0_PIN1 is not used for VSYNC. so i'm a little confused by your question. can you clarify?

for question 2:

for LVDS display we are always using external clock. you can get an accurate clock for your display, but please be noted that the pclk is sharing the same PLL with other modules. without interfering other modules it is not allowed to change the root clock freely. the path is like DPLL->CCM(for clock gating and dividing purpose)->pclk. since you are not allowed to change the DPLL, and CCM does not support fractional division, you can only have the rounded pclk to meet your requirement.

Thanks,

Ray

[SimonFrey]

Hello,

Thanks for the answer Ray Sun.

I have seached for an available DI waveform pin on the display port connector of the QSB and the only one is the DI0_PIN1 in alt mode for the DISP0_SER_SCLK pin. I then looked at the IPU3 driver ipu_disp.c file. Specialy in the ipu_init_sync_panel() function. Here are the DI waveform generated. But my problem is that the first pin DI0_PIN1 is already used for internal vsync generation (i think for anti tearing purpose...) is it posible to move this signal to ane other wave gen and generate my own wave (DDR) instead and keep this anti tearing function?

And i have a second question: I saw that the driver first find a rounded pixel clock function...  the IPU is clocked at 170MHz and i need it between 151 and 162MHz (lcd display datasheet). I founded that the clock is always rounded to 170MHz. Is it right? So is it possible to change the internal IPU clock frequency down to 152MHz? or should i use the external clock??

Thank in advance

Simon Frey

[Yanfei_Sun]

No, the IPU does not support DDR mode. you can refer to the DI waveform settings.