DDR CS1 Boot

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DDR CS1 Boot

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vishakh
Contributor III

Hi,

In our design, we have given a solution based on i.MX6q with 2 GB DDR3 interfaced to MMDC's CS1, without CS0.

As per NXP support team, this method of mounting DDR on CS1 without CS0 is not recommended.

But we still explored options to booting using the above configuration and able to boot the Bootloader with below modifications to the DDR configuration and Bootloader code:

  • Enabled both CS0 and CS1 chip selects with address mirroring enabled.
  • CS0 address space is set from 0x10000000 to 0x50000000 (1GB).
  • CS1 address space is set from 0x50000000 to 0x90000000 (1GB).
  • Bootloader is built to execute from CS1 address space.

We are not able to extend the CS0 and CS1 address space to 2GB boundary (CS0:0x10000000 to 0x90000000. CS1:0x90000000 to end of memory). With this configuration Bootloader doesn't boot from CS1.

Can someone give more information on what is actually happening when we set the MMDC controller with above configuration?

And also we are not able to boot Linux, although we changed the address in Makefile.boot. Are there any other Linux BSP changes to be done?

Thanks and Regards,

Vishakh

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Vishakh

for configuration of CS0 and CS1 address space with 2GB one can refer to

arm2 board (sch-27016)

i.MX6Q/DL 4GB DDR3 RAM porting 

IMX6 surpport 4GB DDR3 reference BRD and length excel 

L4.1.15 arm2 dts file: imx6q-arm2.dts
git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/boot/dts/imx6q-arm2.dts?h=imx_4.1.15_1.0.0_ga
uboot imx_v2015.04 *.cgf file
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx6qarm2?h=imx_v2015.04...

Seems there is no way to use ddr test with DDR on CS1 without CS0,

but for performing test one can replace CS1 with CS0 and run tester on one board.

After finding correct calibration coefficients use them in other boards with DDR on CS1.

Best regards
igor
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