Cortex-M7 NVIC in PIMX8ML8DVNLZAB

[Majidbahmani]

I want to enable NVIC interrupt controller in CM7 of PIMX8ML8DVNLZAB processor. According to “IMX8MPRM reference manual” I used GPIO1_0 to GPIO1_7 to enable INT0-INT7 which are related to IRQ 63 to 56 respectively. Furthermore, I defined GPIO1_Combgfdhined_0_15_IRQHandler as a callback for interrupt event and the pin configuration is as follows:

gpio_pin_config_t exi_config = {kGPIO_DigitalInput , 0, kGPIO_IntRisingOrFallingEdge};

    IOMUXC_SetPinMux(IOMUXC_GPIO1_IO01_GPIO1_IO01, 1U); 

    IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO01_GPIO1_IO01,  IOMUXC_SW_PAD_CTL_PAD_DSE(3U) |

                                          IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |                                              IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

. For  exi_config I have tested all other cases such as kGPIO_IntRisingEdge, kGPIO_IntFallingEdge and I tested both SION enable and disable cases. However, none of these changes works. And I am still unable to use NVIC of CM7. I checked the MCUXpresso SDK for IMX8ML8xxxLZ series and I couldn’t find any input-interrupt example.

Could you please explain if there is any other requirement? I have attached the code. I configured pins in pin_mux.c and enable interrupt controller in test_nvic.c

Please consider that there is another interrupt controller GIC which is available through Linux. I have tested GIC interrupt controller with this code for GPIO3_14 or GPIO1_11 and it works. However, I need the interrupt controller of CM7 (NVIC) which is completely independent of Linux and Cortex-A.

[AldoG]

Hello,

I was looking into your code, and I see that the definition for the interrupt handler have a typo:
GPIO1_Combgfdhined_0_15_IRQHandler instead of GPIO1_Combined_0_15_IRQn

Please try by changing this first,
Best regards,
Aldo.

[Majidbahmani]

Thank you for your response.

Sorry I wanted to know whether I get error if I enter undefined handler, then I forgot to recorrect it. Now I corrected but the problem was not solved.

I have already tested GPIO1_Combined_0_15_IRQHandler for handler according to the link below:

https://mcuxpresso.nxp.com/api_doc/comp/101/i_8mx_2gpio__driver__irq_8c.html 

And I defined IRQ_Type as GPIO1_INTx_IRQn based on the link below:

https://docs.ros.org/en/noetic/api/picovoice_driver/html/group__Interrupt__vector__numbers.html

As you see in the code, I print the value of GPIO1_INTx_IRQn in the first step to make sure that it is equal to the related interrupt in Table7-2 of IMX8MPRM (page 997).

Thank you.

[AldoG]

Hello,

Thank you for checking, as I was looking I notice that GPIO1 block is already in the domain of the Cortex-A so this would make sense that the interrupt is not working correctly, you may take the following post as reference:

https://community.nxp.com/t5/i-MX-Processors/imx8mm-M4-vs-Linux-gpio-interrupt-flag-clear/m-p/981606...

Saludos,
Aldo.

[Majidbahmani]

Hello,

Thank you for your response. Please consider that I have tested on GPIO3 as well. And I disabled the gpio3 in the both u-boot and Linux device trees. Furthermore, I tested the pin as output, and it is controlled through CM7 properly. It seems that the problem is not from accessing GPIO but from assigning a GPIO to NVIC.  Do you know if any other configuration is required in RDC initialization?  

Thanks.