Boot problems with new NAND on mx53

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Boot problems with new NAND on mx53

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paulroy
Contributor I

Hi all

We have to make our iMX53 board boot from a new Cypress - S34ML16G202BHI003 NAND, so we set new parameters for both u-boot and kernel, as:  (datasheet)

 .end_of_table             = false,      
.manufacturer_code        = 0x01,      
.device_code              = 0xd5,      
.cell_technology          = NAND_DEVICE_CELL_TECH_SLC,      
.chip_size_in_bytes       = 2048LL*SZ_1M,      
.block_size_in_pages      = 64,      
.page_total_size_in_bytes = 2*SZ_1K + 128,      
.ecc_strength_in_bits     = 4,      
.ecc_size_in_bytes        = 512,      
.data_setup_in_ns         = 20, //tds      
.data_hold_in_ns          = 10, //tdh      
.address_setup_in_ns      = 25, //tals      
.gpmi_sample_delay_in_ns  = 6,      
.tREA_in_ns               = 30,      
.tRLOH_in_ns              = 0,      
.tRHOH_in_ns              = 15,      
"S34ML16G200",

and after a correct NAND flash, we see we can't boot from NAND, but if we load u-boot with serial download to the board and tell that u-boot boot from kernel partition on new NAND, it boots OK.

So,it seems NAND is working at all, but we are not able to boot from it. Old NAND was an MT29F16G08ABACA, and we boot  OK in same board. So, doubts are:

- do we have to change some other parameters in u-boot to use this new nand? (apart from the ones in struct above)

- should the first bytes seen on nand 0x0000 position change after changing NAND? They look the same, in spite of the change in new NAND geometry.

- could some pull up resistor value soldered in NAND pins (RBB for example) cause this behaviour?.( We have same values for old and new nands)

Any help is appreciated. Thank you.

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4 Replies

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paulroy
Contributor I

Thanks Igor.

I´ve checked and re-checked all BOOT_CFG words, and everything seems to be ok but...no success. I can´t boot from this NAND, but I can write and store data, so problem is not in NAND timings or some other physical parameter of NAND (not even in uboot/Linux source code drivers I think) , but in the way those first bytes are read by ROM code inside MX53 board (or the way i wote them when flashed). 

Somebody told me about enabling/disabling byte swap when NAND uboot partition is flashed, but after testing it nothing changed.

With kobs-ng tool, I get a "bootstream too large" error.so before connecting a JTAG as last resort...,do somebody know if I should also change something in kobs-ng sources to adapt them to my new NAND flash? 

Not really sure if kobs-ng will help with this. If i´m changing NAND geometry (4K+218 to 2K+64)...should change something in NAND first bytes and how would they be written to flash?      

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899 Views
igorpadykov
NXP Employee
NXP Employee
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899 Views
igorpadykov
NXP Employee
NXP Employee

Hi Paul

please refer to Table 7-11. NAND Boot eFUSE Descriptions

i.MX53 Reference Manual

https://www.nxp.com/docs/en/reference-manual/iMX53RM.pdf 

there is no formal support for 2K+128bytes nand geometry.

However seems this Cypress - S34ML16G202BHI003 NAND is multiplane

nand with every plane with 2K+64bytes nand geometry, which is supported.

Please check documentation:

http://www.cypress.com/documentation/datasheets/s34ml01g2-s34ml02g2-s34ml04g2-1-gb-2-gb-4-gb-3-v-4-b...

So seems one can try to set BOOT_CFG1[3:2] Address Cycles 10 - 5,

BOOT_CFG2[7:6] Page Size 01 - 2KB + 64 Bytes (4-bit ECC).

For nand programming please use kobs-ng, please check

https://community.nxp.com/thread/316154
https://community.nxp.com/thread/324232

Also one can try to use mfg tools :
Programmers (Flash, etc.) (3)
IMX_MFG_TOOL
https://www.nxp.com/products/power-management/pmics/power-management-for-i.mx-application-processors...

Best regards
igor
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paulroy
Contributor I

Ok, I´ve seen all NAND has BOOT_CFG2[7:6] as 11 and new one should be 01, I think. So do you know how could I change that?

Thank you.

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