Audio PLL4 clock on iMX6

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Audio PLL4 clock on iMX6

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mmovsisyan
Contributor I

Hi, 

My question is similar to this one, except that it pertains to iMX6 Q processor:

https://community.nxp.com/t5/i-MX-Processors/about-CCM-ANALOG-PLL-AUDIO-xxx-registers-of-i-MX6DL/m-p...

According to Ref Manual PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)

The initial(reset) value of these registers are the following.

 - CCM_ANALOG_PLL_AUDIO[DIV_SELECT]  = 0000110(6 decimal)
 - CCM_ANALOG_PLL_AUDIO_NUM   = 05F5C100h (100 000 000 decimal)
 - CCM_ANALOG_PLL_AUDIO_DENOM   = 2964619Ch (694 444 444 decimal)

Point 1: 

DIV_SELECT range is 27-56. So is the reset value a violation of this? If so, why?

Point 2:

We have functioning I2S interface and audio output. However, all 3 of the above registers are left at their reset values. Using the formula, PLL frequency = 24MHz (6 + 0.144) = 147.456 MHz.

This is out of range of the PLL4 frequencies specified in the reference manual (650-1300 MHz). Isn't the PLL frequency of 147.456MHz we operate at a violation? Like I said there are no issues with the audio output.

Thank you,

Mikael

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art
NXP Employee
NXP Employee

1. By default, the Audio PLL4 is disabled (the CCM_ANALOG_PLL_AUDIO4[ENABLE] bit
is cleared). The application should first appropriately configure the PLL
according to the specifications and only then enable it.

2. See above. Definitely, you have run the ESAI modules not on bare metal
hardware, but under some BSP control. Am I right? If so, the BSP software
initializes the SoC hardware including PLLs in appropriate way on the early boot
stage.

Best Regards,
Artur

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