Applying voltage to IO pins after SoC shutdown

[nija_mankodi]

Hi,

We are developing a board based on 8M Mini dual core SoC MIMX8MM4CVTKZAA.

We have one board to board connector where one SPI port and few GPIOs from SOC are connected. This board to board connector is connected to another board.

Now, we have to shutdown our board when temperature exceeds below thermal threshold. As per our understanding, this shutdown will not be graceful. Now, if SoC goes into shutdown, what will happen if there is still activity on these SPI and GPIOs connected to SoC from another board?

I found below application note that which says that applying voltages to I/O pins when the processor is not powered https://www.nxp.com/docs/en/application-note/AN12130.pdf (Page 7).

How can we protect these SPI and GPIOs from any issue/damage in this case?

[igorpadykov]

Hi nija_mankodi

applying voltage to IO pins is not allowed for i.MX8M as it violates power-up sequence. From

sect.3.2.3 Power supplies usage   i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products

I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This
can cause internal latch-up and malfunctions due to reverse current flows.

AN12130 is for S32K1xx MCUs, not applicable to i.MX.

>How can we protect these SPI and GPIOs from any issue/damage in this case?

one can consider external circuit or buffers which will power-off or isolate external devices.

Or add protection schottky diodes on inputs.

Best regards
igor