About STCK and STFS setting in i.MX6DQ.

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About STCK and STFS setting in i.MX6DQ.

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keitanagashima
Senior Contributor I

Dear All,

The difference was seen STCK and STFS value between Expected and Observed in i.MX6DQ.

Could you tell me the correct setting?

(Device: i.MX6Quad, BSP: L3.14.28)

*Refer to attached file.

======

[Output Result]

  STFS:

    (Expected value) 44.1kHz

    (Observed value) 33.07kHz

  STCK:

    (Expected value) 2.1156MHz

    (Observed value) 2.12MHz

[Input]

  pll4_main_clk : 169.344MHz

[Register Setting]

  SSI1_STCCR

     -DIV2 0b

     -PSR  0b

     -WL   1011b (Number of Bits = 24)

     -DC   00001b

     -PM   000 0000b (Divide by 1)

======

Best Regards,

Keita

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Keita,

   See following , please! The reply is from i.MX Expert team:

t looks like correct in the register settings. But I want to know how the customer to modify the registers and how the customer to use the SSI driver?

In general we only need to pre-caculated which frequency point we need and just set it in Linux driver. For example, for 44.1KHz output, we may configure SSI root clock to 22.5792MHz ( it is a classical frequecy point) and we can calculated PLL4 to 180.6336MHz.

clk_set_rate(&pll4_audio_main_clk, 180633600);

clk_set_parent(&ssi2_clk, &pll4_audio_main_clk);

clk_set_rate(&ssi2_clk, 22579200);

Then we can configure our SSI driver to use 44.1KHz clock and the driver can automatically set the related registers.

Regards,

Weidong

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Keita,

     The cusotmer's operation is correct, but I can't confirm what happened, so I submitted the question to i.MX expert team, Let us wait for their reply!

Regards,

Weidong

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Keita,

   See following , please! The reply is from i.MX Expert team:

t looks like correct in the register settings. But I want to know how the customer to modify the registers and how the customer to use the SSI driver?

In general we only need to pre-caculated which frequency point we need and just set it in Linux driver. For example, for 44.1KHz output, we may configure SSI root clock to 22.5792MHz ( it is a classical frequecy point) and we can calculated PLL4 to 180.6336MHz.

clk_set_rate(&pll4_audio_main_clk, 180633600);

clk_set_parent(&ssi2_clk, &pll4_audio_main_clk);

clk_set_rate(&ssi2_clk, 22579200);

Then we can configure our SSI driver to use 44.1KHz clock and the driver can automatically set the related registers.

Regards,

Weidong

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keitanagashima
Senior Contributor I

Hi Weidong,

Sorry for my delay response.

I could confirm that my customer got the correct frequency!

Thank you very much.

Best Regards,

Keita

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keitanagashima
Senior Contributor I

Hi Weidong,

Thank you for your reply.

OK. I'll confirm it and feedback you.

Best Regards,

Keita

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Keita,

      According to your description, I calculated it like this: 48 x STFS = STCK,  that is 48 x 44.1k = 2.1168MHz, So your STCK should be 2.1168MHz. But now the value you measured is 2.12MHz, I feel the STCK can be considered as correct one.

     According to above  calculating method, if we want to get correct STFS, we should make STCK devided by 48, so please try to configure it !

Regards,

Weidong

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keitanagashima
Senior Contributor I

Hi Weidong,

Do you have any update?

Best Regards,

Keita

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keitanagashima
Senior Contributor I

Hi Weidong,

Thank you for your reply.

According to above calculating method, if we want to get correct STFS,

we should make STCK devided by 48, so please try to configure it !

Refer to excel sheet again.

My customer had already set the STCK divided by 48.

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