ADC_ETC DMA performance

[oayastuy]

Hello everyone,

I'm working on a project where I need to obtain samples from 4 ADC channels at 300KHz.

ARCHITECTURE

To achieve this, I'm utilizing the following peripherals:

• PWM: This peripheral is responsible for triggering the entire sequence. The conversions defined in ADC_ETC are initiated through the VAL0 and VAL1 triggers. The period is set at 60us. I've been trying to lower the period, but doing so disrupts the functionality (Note: When I reduce the period, I also update the delays in the sequences defined in ADC_ETC).

• LPADC1: This peripheral is where the conversions take place. In this case, two commands have been defined, one for reading channel A1_1 and another for reading channel A1_2. The total conversion time of each command is 256.25 ns.

• LPADC2: Similar to LPADC1, this peripheral is used for conversions. Two commands have been defined here as well, one for reading channel A2_3 and another for reading channel A2_4.The total conversion time of each command is 256.25 ns.

• ADC_ETC: This peripheral manages triggers. Four triggers have been defined:

  • Trigger0: This trigger is launched by the PWM VAL0 trigger. It manages the conversions defined in LPADC1. The trigger sequence is as follows:

    1. LPADC1_CMD1
    2. LPADC1_CMD2
    3. WAIT(15us)
    4. LPADC1_CMD1
    5. LPADC1_CMD2
    6. WAIT(15us)
    7. LPADC1_CMD1
    8. LPADC1_CMD2
    9. WAIT(15us)
    10. LPADC1_CMD1
    11. LPADC1_CMD2
  • Trigger1: This trigger is launched by the PWM VAL1 trigger. It manages the conversions defined in LPADC2. The trigger sequence is the same as Trigger0.
  • Trigger4: Synchronized with Trigger0. It manages the conversions defined in LPADC2.
    1. LPADC2_CMD1
    2. LPADC2_CMD2
    3. WAIT(15us)
    4. LPADC2_CMD1
    5. LPADC2_CMD2
    6. WAIT(15us)
    7. LPADC2_CMD1
    8. LPADC2_CMD2
    9. WAIT(15us)
    10. LPADC2_CMD1
    11. LPADC2_CMD2
  • Trigger5: Synchronized with Trigger1. It manages the conversions defined in LPADC2.

• DMA: Once all the conversions are completed, ADC_ETC0COCO0 is generated, initiating the transfer of the conversions. To retrieve all conversions, a transfer of 240 bytes is performed starting from address 0x40048010.

RESULTS

With this configuration, I'm able to perform readings correctly, but it appears that the operation is rather slow:

• It takes approximately 9.65 microseconds from the end of the conversions until the DMA transfer is completed.

• The period is set at 60us. Lowering the period disrupts the functionality (When I decrease the period, I also update the delays in the sequences defined in ADC_ETC). However, if I increase the period, it works correctly. This suggests that there might be some limitation affecting the system.
  

I would greatly appreciate any insights or suggestions on how to improve the performance.

iMXRT1170