irqbalance problem

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irqbalance problem

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Matt3
Contributor I

We use NXP 88W9098 chipset, we found that irq interrupt mainly happened on CPU0 as shown in cat /proc/interrupts
We try to balance the irq on CPU0/CPU1/CPU2/CPU3 by the commands "echo 8 > /proc/irq/392/smp_affinity" and "echo 8 > /proc/irq/394/smp_affinity".
But it shows "write error".
Is there any suggestion about this problem?

 

/ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
392: 2575 0 0 0 MSI 524288 Edge mrvl_pcie_msi
394: 55 0 0 0 MSI 526336 Edge mrvl_pcie_msi


/ # cat /proc/irq/392/smp_affinity
f

/ # cat /proc/irq/394/smp_affinity
f

We can not change the settiing

/ # echo 8 > /proc/irq/392/smp_affinity
sh: write error: Invalid argument

/ # echo 8 > /proc/irq/394/smp_affinity
sh: write error: Invalid argument


Thanks

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8 Replies

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Matt3
Contributor I

Hi Christine,
The host platform is Linux 5.4.179.
The FW version is P109.2. We also try P136.19, but the problem still happened.

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1,734 Views
Matt3
Contributor I

Hi Christine,
The host platform is Linux 5.4.179.
The FW version is P109.2. We also try P136.19, but the problem still happened.

Thanks

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1,724 Views
Christine_Li
NXP TechSupport
NXP TechSupport

Hi, Matt,

I think this issue should be related to host.

Please firstly disable irqbalance with  "service irqbalance stop" or modify "Enable" to 0 in /etc/default/irqbalance ,  then have a try.

And also make sure the probe: /proc/irq/392/smp_affinity has been given written permission.

If not, please chmod "777" to modify file permission then try to echo.

You can also try to modify "smp_affinity_list" to achieve your purpose.

By the way, are you able to modify other irq's  smp_affinity except "88W9098 mrvl_pcie_msi"?

 

Best regards,

Christine.

 

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Matt3
Contributor I

Hi Christine,

1. We are able to modify other irq's smp_affinity
/ # echo 8 > /proc/irq/282/smp_affinity
/ # echo 2 > /proc/irq/284/smp_affinity
/ # echo 4 > /proc/irq/296/smp_affinity
/ # echo 2 > /proc/irq/288/smp_affinity

2. After chmod "777", then modify the mrvl_pcie_msi irq, it still failed.
/ # chmod 777 /proc/irq/392/smp_affinity
/ # echo 8 > /proc/irq/392/smp_affinity
sh: write error: Invalid argument

3. I still can not modify "smp_affinity_list".
/ # echo 8 > /proc/irq/392/smp_affinity_list
sh: write error: Result not representable

any suggestion?

Thanks

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Christine_Li
NXP TechSupport
NXP TechSupport

HI, Matt,

Please help to check whether the irqs that you can modified ​are belongs to host itself.

From my test result, I can only modify the irqs' smp_affinity that belonging to my host platform(i.MX8MQ).

And again, the irq balance mechanism is on the local host side, not controlled by 88W9098.

In default, the irqbalance mechanism is enabled after kernel ​2.4 if your host support SMP.

So don't need to enable irqbalance manually.

NXP 88W9098 chipset's irq interrupt mainly happened on CPU0 because of other irqs happened on other CPUs, the host scheduling mechanism has to assign CPU0 to mrvl_pcie_msi.

From your cat result, we can also see that "smp_affinity" is "f", means, mrvl_pcie_msi can be switched on CPU0,CPU1,CPU2,CPU3.

If you insist to bind 88W9098 to CPU3, may cause performance issue. We don't suggest you do in this way.

 

Best regards,

Christine.

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1,687 Views
Matt3
Contributor I

Hi Christine,

Many thanks for you kind reply.

I still have some question need your help.


NXP 88W9098 chipset's irq interrupt mainly happened on CPU0 because of other irqs happened on other CPUs, the host scheduling mechanism has to assign CPU0 to mrvl_pcie_msi.
Matt: Does it mean that only CPU0 handles the wifi data transfer? how come it does not assign to CPU0,CPU1,CPU2,CPU3 if the value of smp_affinity is f?


From your cat result, we can also see that "smp_affinity" is "f", means, mrvl_pcie_msi can be switched on CPU0,CPU1,CPU2,CPU3.
Matt: from the "/proc/interrupts", it mainly at CPU0, does it switched to other CPU? How to check it switched on CPU0,CPU1,CPU2,CPU3?

Besides, from your experience, do you haven any suggestion for improving wifi performance?


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Christine_Li
NXP TechSupport
NXP TechSupport

HI,Matt,

Please see my reply in line.

Matt: Does it mean that only CPU0 handles the wifi data transfer? how come it does not assign to CPU0,CPU1,CPU2,CPU3 if the value of smp_affinity is f?

==>Christine: No. Which CPU is handling wifi data transfer depends on the host's schedule mechnism. As I mentioned before, the value of smp_affinity is f means the host can assign CPU0,CPU1,CPU2,CPU3 to mrvl_pcie_msi. But which CPU is assigned  actually depends on the host SMP scheduling mechanism. When other irqs are assigned to CPU1,CPU2,CPU3, the CPU0 will be assign to mrvl_pcie_msi. You can check it by "cat /proc/interrupts" to have a look  all of the interrupts.

Matt: from the "/proc/interrupts", it mainly at CPU0, does it switched to other CPU? How to check it switched on CPU0,CPU1,CPU2,CPU3?

==>Christine:I think it will switch to other CPU if CPU0 is too busy and other CPUs are free. You can disable other irqs and cat /proc/interrupts again to reconfirm. In fact I don't recommend you disable irqbalance and bind mrvl_pcie_msi to one fixed CPU.

Besides, from your experience, do you haven any suggestion for improving wifi performance?

==>Christine: WiFi performance strongly depends on RF and hardware. For 88W9098, we have WLAN RF Performance Report on our website. You can download and compare with your test report.If 88W9098 doesn't meet your WiFi performance requirement, please create detail case and provide related logs and reproduce steps to track the root cause. 

Best regards,

Christine.

 

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1,739 Views
Christine_Li
NXP TechSupport
NXP TechSupport

HI, @Tsai Matt (Customer)​ 

May I ask several short questions to better know your issue background?

what's your host platform? Are you using NXP i.MX series(such as i.MX8MQ, i.MX8MM, etc.) or other host?

Is your host OS Linux or Android OS?

What's your kernel version and Wi-Fi Driver/Firmware version?

 

Best regards,

Christine.

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