Can't Read/Write NDEF mesages when NTAG unpowered

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Can't Read/Write NDEF mesages when NTAG unpowered

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pablorp
Contributor I

I have a NHS3152 NTAG that I use with the Android SDK.

 

When it is powered it works correctly:

- The tag is detected as NdefFormatable

- I send the format message

- The tag is detected as Ndef, I can read and write NDEF messages now

 

When it is unpowered it doesn't work:

- The tag is detected as NdefFormatable

- I send the format message

- The tag is stil detected as NdefFormatable, I can't read/write NDEF messages

 

I've seen that the NXP TagWriter is able to write NDEF messages when unpowered (although it can't read NDEF messages), I guess it doesn't use the default Android NFC libraries?

Is there any way to read/write NDEF messages when the device is unpowered?

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driesmoors
NXP Employee
NXP Employee

Hi,

I presume that after "I send the format message"
and before "The tag is stil detected as NdefFormatable, I can't read/write NDEF messages"
you remove the phone and then tap the tag again? This will indeed not work without the support of firmware running on the processor.

The NHS3152 IC uses NFC as a communication channel:

  • When viewed from a tag reader, the NFC memory is just that: memory where you can write NDEF message to.
  • When viewed from the processor in the IC, the NFC memory is just SRAM, where a few interrupts tell the processor when data was read and written.

When you write an NDEF message to the tag, and then unpower the IC, the SRAM contents are gone. When you power the IC again, the firmware running on the Cortex M0+ processor can create his own NDEF message and copy it to the NFC shared memory. That NDEF message can then be read. 

You write an NDEF message to the tag, with the intention that the firmware running on the processor consumes it and interprets it as a command, and then writes his own NDEF message containing the tag 'response', thereby overwriting your 'command'.

The NHS3152 is not a standard tag, it is more than just some external wirelessly accessible memory.  And as such requires dedicated firmware running on the Cortex M0+ that supports your use case,

Kind regards,
Dries.

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