Vybrid TWR-VF65GS10 Alignment fault exception for on-chip sysRAM execution (Cortex-A5 only mode)

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Vybrid TWR-VF65GS10 Alignment fault exception for on-chip sysRAM execution (Cortex-A5 only mode)

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Contributor I

Hi,

I am running code from sysRAM using Cortex-A5 alone with MMU/caches disabled. I get alignment fault data abort when accessing (store instruction) sysRAM memory from strcat() that is not aligned on word boundary. I have following questions regarding  this issue:

1- Doesn't the processor support unaligned sysRAM memory access  even when I have A bit cleared in SCTLR register. Is there any cortex-A5 specific configured required?

2- Is sysRAM on this target un-cacheable. Moreover, can I enable MMU with translation table placed on sysRAM? Currently I am unable to enable MMU from sysRAM.

Solution that can allow hardware unaligned access for sysRAM is preferred rather than needing to change code or using compiler alignment flags. Or I will have to enable externa DDR and then MMU to get rid of these issue?

Thank you!

Best Regards,

Zeeshan Aslam

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NXP Employee
NXP Employee

Hi, this seems quite an old question, please let me know if you are still having problems. There should be no issues with unaligned access, you should be able to select whether the SRAM is cacheable or not.

For specifics on the cores go to -

http://infocenter.arm.com/help/index.jsp

Searching for "a5 mmu" or "a5 alignment" should provide you with links to the relevant information.

Ross

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NXP Employee
NXP Employee

Hi, this seems quite an old question, please let me know if you are still having problems. There should be no issues with unaligned access, you should be able to select whether the SRAM is cacheable or not.

For specifics on the cores go to -

http://infocenter.arm.com/help/index.jsp

Searching for "a5 mmu" or "a5 alignment" should provide you with links to the relevant information.

Ross

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