Latest (Rev.H) Vybrid Tower Module (TWR-VF65GS10) - final schematic and layout + unofficial (practically final) User Manual (now published officially on Freescale 'Vybrid Tower Module (TWR-VF65GS10)' web page as well.)

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Latest (Rev.H) Vybrid Tower Module (TWR-VF65GS10) - final schematic and layout + unofficial (practically final) User Manual (now published officially on Freescale 'Vybrid Tower Module (TWR-VF65GS10)' web page as well.)

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Senior Contributor V
  • Board revision has been validated successfully.
  • Boards will soon be available for purchasing.
  • Presented files currently are in formal process of being published on official company web site.


(Materials attached have been implemented using Cadence tool, both latest Rev.16.6 and older Rev.16.2; use the latter to be converted into different formats or import into other schematic / layout tools.)

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Main Vybrid-related revision modifications (with respect to Rev.G):

  • DDR3: external termination deleted, Vref circuit simplified.
  • Vybrid ballast transistor powered from 1.5V, not 3.3V.
  • Optional "Virtual VF3xx" configuration created.
  • Vybrid Power-On-Reset active timeout made longer to guarantee proper SD card initialization.
  • Optional Ethernet MII interface added (DNP-ed 0-Ohm resistors).
  • Filtering (series ferrite beads) added into x_AFE and x_ADC power rails for better performance.
  • New button SW4 added to test low-power use cases.

 

Please, pay attention to new stackup and material of the board!

(Interestingly enough, one of the reasons for switching to new, high-frequency, board material was need to improve performance of the USB 2.0 interface...)

=====================================================================================================================================

 

For reference only!

 

- Peak-to-peak ripple data for major power rails measured while running video clip included in supplied SD card (board as part of Tower - 2 Elevators + LCD modules powered from Vybrid module):

  • VCC_1V2 (across C103)  - 7.40mV,
  • 1V5_DDR3 (across C51) - 16.83mV,
  • VCC_1V5_SDRAM (across C10) - 18.60mV,
  • VCC_3V3_ADC (across C171) - 4.97mV,
  • VCC_3V3_AFE (across C56) - 10.6mV,
  • VCC_3V3_MCU (across C43) - 10.6mV.


- Preliminary USB and radiation emission data with significant margins.

Original Attachment has been moved to: VYBRID_TWR_DESIGNFILES.zip

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Contributor II

Can you confirm if there have been any corrections regarding debugging locking up on the board?

We had a rev G running some tests connected to a JTAG debug probe and somewhere between every 10 and every 50 times roughly we ran the test the CPU/debug unit would lock up in some unrecoverable state that could only be fixed by power cycling the board. Pressing the board reset button was not enough, and the debug probe could not reach the CPU at all in this state and attempts of debug resets were unsuccessful. This is reproducible on all our boards (some may be older prototype or earlier revisions).

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Senior Contributor I

I suspect that the K20 running the CMSIS-DAP is part of the problem. Since the reset button does not reset the K20, power cycling is the only way to reset it.

I'm considering adding a reset button to the board for the K20. Pin 10 of J2. A simple cable header would do the trick. Or perhaps just wiring it to SW3 pin 3 or 4 so that pressing the existing reset button resets both CPUs.

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Contributor II

Maybe it's possible, but we did not use the K20 debug part, we used an external debug probe.

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Senior Contributor V

Hello Oscar,

At the first glance, based on your information, it does not look like a board-specific issue (you observed it on your board as well), therefore, it makes sense to post this issue in a separate Community thread.

Please, take into account, however, that we officially only support the DS-5 debug tool.

Regards, Naoum Gitnik.

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Contributor III

Hello Naoum,

Thank you for the new design files.  I am currently designing a board based primarily on the Tower Rev. G so I am very interested in the changes brought about in this revision.  I have dug through the .zip files and I don't seem to find the board lay-up drawing.  Is it there and I missed it, or is it available somewhere else?

Thanks and best regards,

Mark Watson

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Senior Contributor V

Hello Mark,

I would also strongly recommend you to use the Vybrid HW Development Guide.

Since it is still on the unofficial, i.e. draft, stage, you may only get it via a Freescale FAE. It is located here - https://community.freescale.com/docs/DOC-101595, but customers have no direct access to it.

You may see what is covers on the i.MX6 one's example.

Regards, Naoum Gitnik.

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Senior Contributor V

Hello Mark,

The layout (*.brd) files are in the VYBRID_TWR_DESIGNFILES.zip package, inside the 2 internal ZIP ones - one for Cadence 16.2, the other for Cadence 16.6.

BTW, all these data are now published officially on the Freescale 'Vybrid Tower Module (TWR-VF65GS10)' web page as well.

Regards, Naoum Gitnik.

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Contributor III

Hello Naoum,

Thank you for the quick response. I did see the .brd files, but I do not have Cadence tools so I am not able to open those files. Previously there was a file, FAB-27442_E.pdf, that showed the board lay-up in PDF format. Is there such a file for the Rev. H board?

Thanks,

Mark Watson

Snowy Range Instruments

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Senior Contributor V

[updated]

Dear Mark,

I discussed your request with my colleagues, and we came to the below conclusion:

- PDFs contain no net names, trace data, constraints, etc., i.e. all the information crucial for high-speed interfaces like USB, DDR, etc., and we prefer to no longer supply them. Instead, we started recommending our customers to use a viewer that 'Cadence' provides for free on their web site, since you and your layout designer may view all the above-mentioned data and essentially copy our approaches; as far as I know, the viewer has an option to generate PDFs as well, if you still need them.

Sincerely, Naoum Gitnik.

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Contributor III

Dear Naoum,

Thank you. I should have thought to look at Cadence for the viewer. Has the Rev. H actually been tried yet, or should I base my design on the Rev. G boards that are shipping? I have requested the HW Design Guide via our FAE and I hope to see it soon.

Mark

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Senior Contributor V

Dear Mark,

The Rev.H has been fully validated and will be offered to the customers in the nearest future.

Compared to the Rev.G, it has been improved significantly + all the settings in the SW code supplied with it, especially the DDR ones, are optimized for the Rev.H layout.

Regards, Naoum Gitnik.

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Contributor III

Dear Naoum,

Good morning. The Cadence freeware tools work just fine for taking a look at the layout. I am wondering if Gerber files are available for the Rev. H. I was hoping to import them on unused layers and then copy the processor to DDR3 section verbatim to prevent any possible timing issues.

Thanks,

Mark

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Senior Contributor V

Dear Mark,

Unfortunately, as I have been instructed, we do not provide Gerber files. Please, if possible, try generating them using the Cadence viewer.

Regards, Naoum Gitnik.

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