T1042 HRESET held low after PORESET

[akowalczyk]

Hello!

We are bringing up a custom board with a T1042NXE7PQB and running into an issue with asserting PORESET from Linux. In an auto-boot scenario the board works fine, HRESET goes high as expected, and the system boots into Linux. However, when we send the command to reboot from Linux, the PORESET signal goes low for the expected 1.5ms, and HRESET goes low, but does not come back up.

We have a CPLD monitoring the state of HRESET but I have confirmed it is a tri-state input only, and does not actuate the HRESET signal at all. We have other circuitry conneted to HRESET through an open drain buffer, and I have confirmed this is not asserting at any point during this sequence. The CPLD monitors RESET_REQ_EN and passes that info to PORESET once the rest of the system is stable, I have confirmed that the assertion of RESET_REQ_EN causes the necessary reset signal on PORESET to start that process.

Is there any reason the T1042 would hold HRESET low and not exit reset differently for a reset after boot vs the expected reset sequence during power-up? I've attached a scope shot of the behavior, CH1 (yellow) is HRESET, CH2 (blue) is PORESET

Thank you!

A. Kowalczyk

[LFGP]

please considere the next note (datasheet extracted) :
>>
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed.
>>

review the datasheet for more details.