MMA8451QR1

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MMA8451QR1

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thipp
Contributor I

Is there a block diagram for the pin structure of the INT pins?  Are they OD or totem pole? If there are internal PU/PD resistors what are the values?

I am trying to understand if there is a backfeed path from INT1 or INT2 back to VDD or VDDIO when VDD/VDDIO are high impedance and there is an external voltage on INT1 or INT2.

What kind of current can be tolerated in this condition?

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Terry,

The INT pins can be configured using the PP_OD bit to be push-pull (PP_OD = 0 - default) or open drain (PP_OD = 1).

The polarity of the INT pins can be configured using the IPOL bit. The default value is active low (IPOL = 0) meaning any interrupt event is signaled with a logical 0.

PS: Note that the MMA8451QR1 is in “End of Life” status and we recommend either the FXLS8974CF or FXLS8967AF as a replacement.

BR, Tomas

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TomasVaverka
NXP TechSupport
NXP TechSupport

Hello Terry,

The INT pins can be configured using the PP_OD bit to be push-pull (PP_OD = 0 - default) or open drain (PP_OD = 1).

The polarity of the INT pins can be configured using the IPOL bit. The default value is active low (IPOL = 0) meaning any interrupt event is signaled with a logical 0.

PS: Note that the MMA8451QR1 is in “End of Life” status and we recommend either the FXLS8974CF or FXLS8967AF as a replacement.

BR, Tomas

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