WDG interrupt with RTD AUTOSAR 4.4

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WDG interrupt with RTD AUTOSAR 4.4

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HectorNadal
Contributor I

Dear NXP community,

I´m working with NXP S32K144 micro and RTD AUTOSAR 4.4

After configuring RTD all seems to be OK, WDG resets are generated at the time expected, but the problem is that interrupts are not launched. 

You can see the register value in the picture attached.  

In order to force the WDG reset I commented the call to  Wdg_ChannelSetTriggerCondition(WDG_IPW_INSTANCE0, Timeout) at  Wdg_43_Instance0.c

Am I doing something wrong?

Could you help me?

Thanks in advance!

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VaneB
NXP TechSupport
NXP TechSupport

Hi @HectorNadal 

On WDOG timeout, the WDOG module immediately requests a reset in the Reset Control Module (RCM). So, if the WDOG counter is not refreshed, its interrupt triggers a reset. 

VaneB_0-1693511761807.png

The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or becomes pending in NVIC. After the delay, the reset is requested in RCM.

If you want to force a reset, set the Wdg Trigger Condition (Wdg_43_Instance0_SetTriggerCondition) just once to generate a timeout. 

 

B.R.

VaneB

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HectorNadal
Contributor I

Hi @VaneB,

Thanks for your answer.

Maybe I din´t explained the issue properly. 

WDG is generating the reset but interrupt handler is not called. I have tried to change interrupt clase to 0 but it´s not called anyway. 

Could you help me?

Thanks. 

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VaneB
NXP TechSupport
NXP TechSupport

Hi @HectorNadal 

If in Watchdog Control and Status Register (CS), you have Watchdog Interrupt (INT) equal to 0, the reset request is immediately generated, so you will not be able to see the Watchdog Interrupt Flag. 

As I mentioned before, you can delay the Watchdog resets by 128 bus clocks from the interrupt vector fetch.

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