S32K312 download flash and reset.

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S32K312 download flash and reset.

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rexoplans
Contributor III
 

Hello, I am using an S32K312 processor. I am running code with an RTOS on my processor. When I flash the code directly, I notice that it keeps resetting, but there is no problem when I connect in debug mode. I understand that it is resetting from the LEDs connected to my regulators. Where can I see the reason for the reset

 

 

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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @rexoplans,

You could try to check the MC_RGM register and observe the functional reset register value.

This is usually a clock settings issue. Please check AIPS_SLOW_CLK and HSE_CLK values. Also check DCM record regarding HSE_CLK_MODE_OPTION. With this, you know the ratio (either 1:2 or 1:4) that those clocks shall comply with.

You can test configurations from the S32K3 Reference Manual chapter 24.7.2 (System clocking configurations) and confirm if the issue persists.

Best regards,
Julián

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rexoplans
Contributor III
@Julián_AragónM What is the wrong my config ? (Configuration settings are specified.)
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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @rexoplans,

Please make sure you are not going over the limitations from Table 144:

Julin_AragnM_0-1721422631509.png

There are also some clock configuration options in Table 145. (System clocking configurations). I would suggest configuring one of these options and testing the code.

This community post may be relevant: Solved: S32K311 can not work normally without debugger - NXP Community. The solution was also the HSE_CLK configured incorrectly.

Best regards,
Julián

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rexoplans
Contributor III
@Julián_AragónM Thank you for response. I noticed discrepancies between the frequency in the CMU reference (the MonitoredClockFrequency value in the Clock_Ip_CmuConfigType struct) and Table 145. I plan to change it and test it tomorrow. What I don't understand is that I've been working with this board for about a year, and I only started getting this error recently. I was getting it 4 months ago, but after fixing an overflow issue, I thought this error was resolved. In fact, when I disable certain init functions (e.g., HSE init) or reduce the logs I print for debugging during startup, I see that this issue disappears. Honestly, I have no doubt about what you said; I just don't understand what gets affected when I make those changes. I'm suspicious of the clock configuration because my CAN speed is higher than expected. (When I calculate it for 12 MHz, it gives a CAN baud rate of 15.7). On the other hand, it was working for a long time. I really don't get it.
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Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @rexoplans,

Have you installed a new version for the IDE or RTD recently? Or maybe is there a configuration in Clock Tool that overwrites your configuration every time the code is updated? It is hard to tell from only this information.

 

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rexoplans
Contributor III
{
.Name = AIPS_PLAT_CLK,
.Enable = 0U,
.Interrupt = (CMU_FC_IER_FLLIE(0U) |
CMU_FC_IER_FHHIE(0U) |
CMU_FC_IER_FLLAIE(0U) |
CMU_FC_IER_FHHAIE(0U)),
.MonitoredClockFrequency = 60000000U,
.Indexes = {0U,0U,},
},

{
.Name = HSE_CLK,
.Enable = 0U,
.Interrupt = (CMU_FC_IER_FLLIE(0U) |
CMU_FC_IER_FHHIE(0U) |
CMU_FC_IER_FLLAIE(0U) |
CMU_FC_IER_FHHAIE(0U)),
.MonitoredClockFrequency = 60000000U,
.Indexes = {0U,0U,},
}, this is my Clock monitoring config. Also, my dividers values 2 or 4. And, Clock_Ip_SelectorConfigType values = {
.Name = SCS_CLK,
.Value = PLL_PHI0_CLK,
},

{
.Name = CLKOUT_RUN_CLK,
.Value = FIRC_CLK,
},

{
.Name = CLKOUT_STANDBY_CLK,
.Value = FIRC_CLK,
},

{
.Name = FLEXCANA_CLK,
.Value = FIRC_CLK,
},

{
.Name = FLEXCANB_CLK,
.Value = FIRC_CLK,
},

{
.Name = RTC_CLK,
#ifdef INTERNAL_SIRC_USES
.Value = SIRC_CLK,
#endif /* INTERNAL_SIRC_USES */
#ifdef EXTERNAL_FXOSC_USES
.Value = FXOSC_CLK,
#endif /* EXTERNAL_FXOSC_USES */
#ifdef EXTERNAL_FIRC_USES
.Value = FIRC_CLK,
#endif /* EXTERNAL_FIRC_USES */
},

{
.Name = STMA_CLK,
.Value = FIRC_CLK,
},

{
.Name = TRACE_CLK,
.Value = FIRC_CLK,
},
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