S32K3 flash: do some caches/buffers need to be invalidated after programming flash memory (c40asf)?

[ferencvalenta]

From the manual:

"Flash core reads are performed through the PFC BIU. In many cases, the BIU does read page buffering to allow sequential reads to be done with higher performance. This could provide a data coherency issue that must be handled with software. Data coherency may be an issue after a program or erase operation, as well as UTest NVM sector operations."

What exactly needs to be done after program/erase to be able to read back the new content immediately? I invalidate the CPU cache, and it seems to be working. Earlier there were specific procedures to invalidate the page buffers in PFLASH, the buffers in BIU etc... in earlier devices like the MPC5748G.

Do the same procedures apply to the S32K3 family?

[ferencvalenta]

Hi David,

You mean that the CBFEN and/or DBFEN bits should be cleared BEFORE programming, and and set again AFTER programming? Okay, that can be done. I'm also invalidating the CPU data cache for the programmed area through CMSIS.

For Calypso, it was more complicated! You had to start a programming sequence and set the PGM bit in MCR, but instead of going forward with setting EHV too, PGM had to be cleared to return to normal mode. For BIU, an address at least 32 bytes higher or lower had to be read to flush the buffer. Plus the CPU cache. Seems to be easier now.

[davidtosenovjan]

Yes, it is basically the same.

Cache should be disabled before flash programming and invalidated during re-enablement.