S32K146 SPI Master - clock irregularities

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S32K146 SPI Master - clock irregularities

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gary2
Contributor I

We have a S32K146 running as an SPI master, at 4Mbps, DMA and transferring around 500 bytes per frame.

Often, at each 32nd bit multiple of data transfer, the bit is sometimes incorrect.

Looking on a 'scope, the S32K generated SPI clock, is truncated, during its high period (from 125ns to 62ns). This happens every 32 bits, consistantly. The clock appears perfect in every other respect, with no delays/stalling etc.

Is this a known issue, incorrect SPI setup (we are using AutoSar), or something else?

 

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namnguyenviet
NXP Employee
NXP Employee

Hi,

Could you please provide us your SPI configuration? 

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