This is where I am so far:
#include "device_registers.h" /* include peripheral declarations */
#include "LPSPI.h"
#include "clocks_and_modes.h"
#include <stdio.h>
#include <stdint.h>
uint16_t x,y,z;
float xg, yg, zg;
uint16_t X_raw, Y_raw, Z_raw;
int i;
uint8_t rx_buffer[6];
void WDOG_disable (void)
{
WDOG->CNT=0xD928C520; /* Unlock watchdog */
WDOG->TOVAL=0x0000FFFF; /* Maximum timeout value */
WDOG->CS = 0x00002100; /* Disable watchdog */
}
void PORT_init (void)
{
/*!
* Pins definitions
* ===================================================
*
* Pin number | Function
* ----------------- |------------------
* PTB14 | LPSPI1_SCK
* PTB15 | LPSPI1_SIN
* PTB16 | LPSPI1_SOUT
* PTB17 | LPSPI1_PCS3
*/
PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B2: MUX = ALT3, LPSPI1_SCK */
PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B3: MUX = ALT3, LPSPI1_SIN */
PORTB->PCR[4]|=PORT_PCR_MUX(3); /* Port B4: MUX = ALT3, LPSPI1_SOUT */
// PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[5] = 0x00000100; /* Port B5: MUX = GPIO */
PTB->PDDR |= 1<<5; /* Port B5: Data Direction= output */
PTB->PTOR |= 1<<5; /* toggle output port B5 */
PTB-> PSOR |= (1 << 5);
}
int main(void)
{
uint32_t counter = 0;
WDOG_disable(); /* Disable WDOG */
SOSC_init_8MHz(); /* Initialize system oscillator for 8 MHz xtal */
SPLL_init_160MHz(); /* Initialize SPLL to 160 MHz with 8 MHz SOSC */
NormalRUNmode_80MHz(); /* Init clocks: 80 MHz sysclk & core, 40 MHz bus, 20 MHz flash */
LPSPI1_init_master(); /* Initialize LPSPI 1 as master */
PORT_init(); /* Configure ports */
LPSPI1_write_addresses(0x31, 0x0f);
LPSPI1_write_addresses(0x2d, 0x08);
for(;;)
{
receiveBytes(&rx_buffer, 6);
x = ((rx_buffer[1]<<8)|rx_buffer[0]);
y = ((rx_buffer[3]<<8)|rx_buffer[2]);
z = ((rx_buffer[5]<<8)|rx_buffer[4]);
counter++;
}
}
this is the main I'm using
Now to the LPSPI:
/*
* Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2018, NXP.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "device_registers.h" /* include peripheral declarations */
void LPSPI1_init_master(void)
{
/*!
* LPSPI1 Clocking:
* ===================================================
*/
PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = PCC_PCCn_PR_MASK /* (default) Peripheral is present. */
|PCC_PCCn_CGC_MASK /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
|PCC_PCCn_PCS(6);
/*!
* LPSPI1 Initialization:
* ===================================================
*/
LPSPI0->CR = 0x00000000; /* Disable module for configuration */
LPSPI0->IER = 0x00000000; /* Interrupts not used */
LPSPI0->DER = 0x00000000; /* DMA not used */
LPSPI0->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */
LPSPI0->CFGR1 = LPSPI_CFGR1_MASTER_MASK /* Configurations: master mode */
|LPSPI_CFGR1_AUTOPCS(0);
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */
LPSPI0->TCR = LPSPI_TCR_CPHA_MASK
// |LPSPI_TCR_WIDTH (16)
|LPSPI_TCR_PRESCALE(2)
// |LPSPI_TCR_PCS(1)
|LPSPI_TCR_CPOL(1)
|LPSPI_TCR_FRAMESZ(7); /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc */
/* CPOL=0: SCK inactive state is low */
/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge */
/* PRESCALE=2: Functional clock divided by 2**2 = 4 */
/* PCS=3: Transfer using PCS3 */
/* LSBF=0: Data is transfered MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=15: # bits in frame = 15+1=16 */
LPSPI0->CCR = LPSPI_CCR_SCKPCS(4)
|LPSPI_CCR_PCSSCK(4)
|LPSPI_CCR_DBT(8)
|LPSPI_CCR_SCKDIV(8); /* Clock dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
// LPSPI0->FCR = LPSPI_FCR_TXWATER(3); /* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI0->CR = LPSPI_CR_MEN_MASK
|LPSPI_CR_DBGEN_MASK; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
}
void LPSPI1_write_addresses(uint8_t address, uint8_t command) { // works like a charm
address = address|0x40; // multibyte write enabled
// address = address|0x80; // multibyte write enabled
PTB-> PCOR |= (1 << 5); // CS LOW
while ((LPSPI0->SR & LPSPI_SR_TDF_MASK) >> LPSPI_SR_TDF_SHIFT == 0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = address; /* Transmit address 1 */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
while ((LPSPI0->SR & LPSPI_SR_TDF_MASK) >> LPSPI_SR_TDF_SHIFT == 0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = command; /* Transmit address 2 */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
PTB-> PSOR |= (1 << 5); // CS HIGH
}
void receiveBytes(uint8_t *buffer, uint8_t numBytes)
{
uint8_t i;
PTB->PCOR |= (1 << 5); // CS LOW
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0) {}
LPSPI0->TDR = LPSPI_TDR_DATA(0xf2) ;
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0){}
LPSPI0->RDR ;
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
for (i = 0 ; i < numBytes; ++i) {
while ((LPSPI0->SR & LPSPI_SR_TDF_MASK) >> LPSPI_SR_TDF_SHIFT == 0) {}
LPSPI0->TDR = LPSPI_TDR_DATA(0x00);
while ((LPSPI0->SR & LPSPI_SR_RDF_MASK) >> LPSPI_SR_RDF_SHIFT == 0) {}
buffer[i] = LPSPI0->RDR;
}
// LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
// while((LPSPI0->SR & LPSPI_SR_TCF_MASK)>>LPSPI_SR_TCF_SHIFT==0) {}
// LPSPI0->SR |= LPSPI_SR_TCF_MASK;
PTB->PSOR |= (1 << 5); // CS HIGH
}
Now the LPSPI1_write_addresses function works pretty good, I am now able to send the 2 addresses while controlling the CS pin and I can see that on the Scope too.
but the Problem here is also happening in the loop of the receiveBytes function where the code crashes and gives me the same "Pointer issue".
but I cant seem to figure out why.
Any suggestions?
I also get this error in the console:
BusFault: An imprecise (asynchronous) data access error has occurred.
HardFault: A fault has been escalated to a hard fault.
Thanks in advance for your help
