S32K144 SPI interface

[AnilKumar409]

Hi,

I'm implemented the LPSPI in master(LPSPI1) and slave modes (LPSPI0) by initializing ports(D,B). But I was not able to build the communication. I'm attaching the code. Please have a look and suggest me.

/*
* main implementation: use this 'C' sample to create your own application
*
*/
#include "S32K144.h"
#include "Clock_modes.h"

uint16_t tx_16bits = 0xFD00;
uint16_t LPSPI1_16bits_read; /* Returned data in to SPI */
uint16_t LPSPI0_16bits_read; /* Returned data in to SPI */

void PORT_init(){
//Master:
PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
PORTD->PCR[0] |= PORT_PCR_MUX(3); /*Port D0: MUX = ALT3, SCK*/
PORTD->PCR[1] |= PORT_PCR_MUX(3); /*Port D1: MUX = ALT3, SIN*/
PORTD->PCR[2] |= PORT_PCR_MUX(3); /*Port D2: MUX = ALT3, SOUT*/
PORTD->PCR[3] |= PORT_PCR_MUX(3); /*Port D3: MUX = ALT3, PCS0*/

// Slave
PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK;
PORTB->PCR[2] |= PORT_PCR_MUX(3); /*Port B2: MUX = ALT3, SCK*/
PORTB->PCR[3] |= PORT_PCR_MUX(3); /*Port B1: MUX = ALT3, SIN*/
PORTB->PCR[1] |= PORT_PCR_MUX(3); /*Port B1: MUX = ALT3, SOUT*/
PORTB->PCR[0] |= PORT_PCR_MUX(3);

}
void LPSPI1_init_master(void) {
PCC->PCCn[PCC_LPSPI1_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI1_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */

LPSPI1->CR = 0x00000000; /* Disable module for configuration */
LPSPI1->IER = 0x00000000; /* Interrupts not used */
LPSPI1->DER = 0x00000000; /* DMA not used */
LPSPI1->CFGR0 = 0x00000000; /* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */
LPSPI1->CFGR1 = 0x00000001; /* Configurations: master mode*/
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */
/* PINCFG=0: SIN is input, SOUT is output */
/* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */
LPSPI1->TCR = 0x5300000F; /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc*/
/* CPOL=0: SCK inactive state is low */
/* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/
/* PRESCALE=2: Functional clock divided by 2**2 = 4 */
/* PCS=3: Transfer using PCS3 */
/* LSBF=0: Data is transfered MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=15: # bits in frame = 15+1=16 */
LPSPI1->CCR = 0x04090808; /* Clock dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
LPSPI1->FCR = 0x00000003; /* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI1->CR = 0x00000009; /* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */

}
void LPSPI0_init_slave(void) {
PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */

LPSPI0 -> CR = 0x00000000;
LPSPI0 -> CFGR0 = 0x00000000;
LPSPI0 -> CFGR1 = 0x00000004;/* PCSCFG=1: PCS[3:2] are disabled */
/* AUTOPCS=1: does not apply for master mode */
LPSPI0->FCR = 0x00000003; /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI0 -> TCR = 0x4000000F; /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/
/* FRAMESZ=15: # bits in frame = 15+1=16 */
LPSPI0 -> CR = 0x00000009;/* DBGEN=1: module enabled in debug mode */
/* MEN=1: Module is enabled */

}

void LPSPI1_tx_16bits (uint16_t send) {
while((LPSPI1->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI1->TDR = send; /* Transmit data */
LPSPI1->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */

}

void LPSPI0_tx_16bits (uint16_t send) {
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = send; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

uint16_t LPSPI1_rx_16bits (void) {
uint16_t recieve = 0;

while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve|= LPSPI1->RDR; /* Read received data */
LPSPI1->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
return recieve; /* Return received data */
}

uint16_t LPSPI0_rx_16bits (void) {
uint16_t recieve = 0;

while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve= LPSPI0->RDR; /* Read received data */
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
return recieve; /* Return received data */
}
int main(void) {
uint32_t cnt = 0;
WDOG_disable();
SOSC_init_8MHz();
SPLL_init_160MHz();
NormalRunMode_80MHz();
LPSPI1_init_master();
LPSPI0_init_slave();
PORT_init();
for (;;) {
LPSPI1_tx_16bits(tx_16bits);
LPSPI0_tx_16bits(tx_16bits);
LPSPI1_16bits_read = LPSPI1_rx_16bits();
LPSPI0_16bits_read = LPSPI0_rx_16bits();
cnt++;
}
return 0;
}

[AnilKumar409]

hello @danielmartynek 

It's working Thank you..

[danielmartynek]

Hello @AnilKumar409,

At the time the Master starts the transfer, the Slave TX buffer must be filled with data.

Try calling

LPSPI0_tx_16bits(tx_16bits);

before

LPSPI1_tx_16bits(tx_16bits);

BR, Daniel