S32K144 LPSPI Rx FIFO issue

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S32K144 LPSPI Rx FIFO issue

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kentseng
Contributor II

Dear Sir.

I design a BMS with S32K144 and MC33664,

so I should open LPSPI0 (Master)and LPSPI1 (Slave),

TPL communication once 5 bytes,

after transmit 40-bit data, LPSPI1 using "while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);"

but in the debug mode , MCU will stop on here. i have no ideal for this.

and how to read the Rx FIFO, if over 1 word.i just read the last 32bits

u32 SPIRxReadBytes(u8 *u8Data, u8 maxBytes)
{
u32 u8BytesRead;
u8BytesRead = 0;
u8Data = u8Data+maxBytes; // set pointer to end of buffer
while((LPSPI1->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
u8BytesRead= LPSPI1->RDR; /* Read received data */
LPSPI1->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */


return u8BytesRead; /* Return received data */
}

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello kentseng,

I have difficulties to understand the issue.

Do you read the RX FIFO of the master? The FSR register provides the number of words stored in the RX FIFO.

The master stall the operation when the receive FIFO is full unless CFGR1_NOSTALL is set.

Do you see any errors in the LPSPI_SR register?

Could you please attach a test project?

Thank you,

BR, Daniel

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