Hello Daniel,
After reset or wakeup from deep sleep (soft reset MCORE_SCS_AIRCR = 0x05FA0004) we are calling FlexNVM parttion command to check partition and also calling Ftfc_Eep_Ip_Init api which is in Ftfc_Eep_Ip.c file.
This api take care of brownout code with quick write and EEERDY bit.
Regarding LVD handler if you have any code then please share.
We are checking CCIF bit `before each read write operation for each byte.
return code is 0x03 when CCIF not set (any pending opertion is there). Also before entering into deep sleep we check CCIF bit set and then enter sleep.
/*==================================================================================================
Function : NVM_Hal_Write_Eep
Description : Write one or more complete eeprom pages to the eeprom device
Parameter : start_add, *data_buf, size
Return value : return write_status;
FTFC_EEP_IP_STATUS_OK = 0x00 < success >
FTFC_EEP_IP_STATUS_FAILED = 0x01 < failure >
0x03 <CCIF==0>
Remarks : none
==================================================================================================*/
uint8 NVM_Hal_Write_Eep(uint32 start_add, uint8 *data_buf, uint16 size)
{
uint16 crc=0xFFFF;
uint8 write_status = 0x01,read_status = 0x01, read_buf[size], crc_buf[2]={0};
/* calculate crc */
crc=I2C_HAL_Calculate_CRC16_ccitt(data_buf, (size));
/* At the end of data buffer add 2 bytes of calculated CRC */
crc_buf[0] = (uint8)((crc >> & 0xFF);
crc_buf[1] = (uint8)crc;
if(0U != (IP_FTFC->FSTAT & 0x80))
{
/* Write one or more complete eeprom pages to the eeprom device */
for(i=0; (i<(size)) && ( 0U != (IP_FTFC->FSTAT & 0x80)); i++)
{
retJobResultType = Ftfc_Eep_Ip_Write(start_add + i, data_buf + i, FTFC_EEP_IP_PAGE_BYTE, FALSE);
}
if(FTFC_EEP_IP_STATUS_OK == retJobResultType)
{
for(i=0; (i< 2U) && ( 0U != (IP_FTFC->FSTAT & 0x80)); i++)
{
Ftfc_Eep_Ip_Write(start_add + size + i, crc_buf + i, FTFC_EEP_IP_PAGE_BYTE, FALSE);
}
}
if(FTFC_EEP_IP_STATUS_OK == retJobResultType)
{
read_status = NVM_Hal_Read_Eep(start_add, read_buf, size);
if( FTFC_EEP_IP_STATUS_OK == read_status )
{
write_status = FTFC_EEP_IP_STATUS_OK;
}
}
}
else{
write_status = 0x03;
}
return (write_status);
}
/*==================================================================================================
Function : NVM_Hal_Read_Eep
Description : Reads from eeprom memory
Parameter : start_add, *read_buf, size
Return value : return read_status
FTFC_EEP_IP_STATUS_OK = 0x00 < success >
FTFC_EEP_IP_STATUS_FAILED = 0x01 < failure >
0x03<CCIF==0>
Remarks : none
==================================================================================================*/
uint8 NVM_Hal_Read_Eep(uint32 start_add, uint8 *read_buf, uint16 size)
{
uint16 crc=0xFFFF;
uint8 crc_msb = 0, crc_lsb=0, read_status = 0x01;
uint8 myRead_buf[size];
if(0U != (IP_FTFC->FSTAT & 0x80))
{
/* Reads from eeprom memory */
for(i=0; (i<(size + 2U)) && ( 0U != (IP_FTFC->FSTAT & 0x80)); i++)
{
retJobResultType = Ftfc_Eep_Ip_Read(start_add + i, myRead_buf + i, FTFC_EEP_IP_PAGE_BYTE);
}
/* Calculate CRC if read success */
if(FTFC_EEP_IP_STATUS_OK == retJobResultType)
{
crc=I2C_HAL_Calculate_CRC16_ccitt(myRead_buf, size);
crc_msb=(uint8)(crc >> 8 & 0xFF); /* upper 8 bits of crc */
crc_lsb=(uint8)crc; /* lower 8 bit of crc */
if((myRead_buf[size]!=0xFF) && (myRead_buf[size+1]!=0xFF))
{
/* compare lower 8 bit and upper 8 bit of calculated crc with buf's last 2 bytes */
if((myRead_buf[size] != crc_msb) && (myRead_buf[size + 1] != crc_lsb))
{
for(i=0; i < size; i++)
{
myRead_buf[i] = 0xFF;
}
read_status = FTFC_EEP_IP_STATUS_FAILED; /* return status as fail if read CRC not match with calculated CRC */
}
else
{
read_status = FTFC_EEP_IP_STATUS_OK;
}
}
else
{
read_status = FTFC_EEP_IP_STATUS_OK; /* 1st power on data will be all FF, read status =success */
}
}
else
{
read_status = FTFC_EEP_IP_STATUS_FAILED;
}
for(i=0; i < size; i++)
{
read_buf[i] = myRead_buf[i];
}
}
else{
read_status = 0x03;
}
return read_status;
}
/*************************************************************************************************************************************************************/
Ftfc_Eep_Ip_StatusType Ftfc_Eep_Ip_Init (Ftfc_Eep_Ip_ConfigType const * pConfig)
{
Ftfc_Eep_Ip_StatusType Status = FTFC_EEP_IP_STATUS_OK;
uint8 BrownoutCode = 0U;
FTFC_DEV_ASSERT(NULL_PTR != pConfig);
/* Overwrite all global variables */
Ftfc_Eep_Ip_pxConfiguration = pConfig;
Ftfc_Eep_Ip_eBrownOutCode = FTFC_EEP_IP_NO_BO_DETECTED;
Ftfc_Eep_Ip_xAsyncJob.TicksStarted = 0U;
Ftfc_Eep_Ip_xAsyncJob.TicksElapsed = 0U;
Ftfc_Eep_Ip_xAsyncJob.Result = FTFC_EEP_IP_STATUS_OK;
if (0U == (IP_EEPROM->FCNFG & FCNFG_EEERDY_MASK))
{
/* When the memory partitioning is done without the option to load the EEPROM data
* to FLEXRAM at reset, a FLEXRAM_FCC_MODE_EEERAM_NORMAL command is needed (so EEERDy gets set).
* Also, the FLEXRAM_FCC_GET_FLEXRAM_STATUS cmd is not allowed unless the EEERDY bit is set. */
Status = Ftfc_Eep_Ip_CmdSetFlexramFunction(FLEXRAM_FCC_MODE_EEERAM_NORMAL, 0U);
}
if (FTFC_EEP_IP_STATUS_OK == Status)
{
Status = Ftfc_Eep_Ip_CmdSetFlexramFunction(FLEXRAM_FCC_GET_FLEXRAM_STATUS, 0U);
if (FTFC_EEP_IP_STATUS_OK == Status)
{
BrownoutCode = IP_EEPROM->FCCOB[FTFC_EEP_IP_FCCOB_SETRAM_READ_BROWNOUT_CODE];
switch (BrownoutCode)
{
case FTFC_EEP_IP_BO_DURING_MAINTENANCE_U8:
Ftfc_Eep_Ip_eBrownOutCode = FTFC_EEP_IP_BO_DURING_MAINTENANCE;
break;
case FTFC_EEP_IP_BO_DURING_QUICK_WRITES_U8:
Ftfc_Eep_Ip_eBrownOutCode = FTFC_EEP_IP_BO_DURING_QUICK_WRITES;
break;
case FTFC_EEP_IP_BO_DURING_NORMAL_WRITES_U8:
Ftfc_Eep_Ip_eBrownOutCode = FTFC_EEP_IP_BO_DURING_NORMAL_WRITES;
break;
case FTFC_EEP_IP_NO_BO_DETECTED_U8:
Ftfc_Eep_Ip_eBrownOutCode = FTFC_EEP_IP_NO_BO_DETECTED;
break;
default:
Status = FTFC_EEP_IP_STATUS_FAILED;
break;
}
if (FTFC_EEP_IP_NO_BO_DETECTED != Ftfc_Eep_Ip_eBrownOutCode)
{
Status = Ftfc_Eep_Ip_CmdSetFlexramFunction(FLEXRAM_FCC_COMPLETE_MAINTENANCE, 0U);
}
}
}
return Status;
}
