MCU is resetting when running without debugger.

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MCU is resetting when running without debugger.

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ManuSharma
Contributor I

Hi,

I am observing continues MCU reset when i am running my software with out debugger but with debugger no reset is observed.

Changes performed in Software:  I have migrated my MCAL RTD driver from SW32K3_RTD_4.4_2.0.1 to SW32K3_S32M27x_RTD_R21-11_4.0.0_P01.

Issue :  After performing the migration i am observing the MCU reset continuously when i am running the software with out debugger but with debugger NO reset observed.

Observation :

1.Check the MC_RGM register and observe the functional reset register value is set to HSE_SWT_RST which is majorly because of external clock issue as per my understanding. 

2. While performing the migration i observed that external slow clock SXOSC is removed from the tresos configuration, There is not container for SXOSC clock.

3. Checked the MCU.xdm file in that SXOSC section is available but when i loading the XDM file containers are not coming on tresos.

Kindly let know how i can solve this issue of reset.

Thanks & Regards

Manu Sharma

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3 Replies

138 Views
ManuSharma
Contributor I

Hi Julian,

Thank you for you support.

After changing the HSE_CLK to 60MHZ which is half of the core clock(120MHZ). Previously it was configured to 120MHZ.

After doing the above step reset is not observed with out the debugger as well.

But i am still confused why previously it was not resetting with debugger connected? please help me to understand this behavior.

Thanks & Regards

Manu Sharma

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102 Views
Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @ManuSharma,

I'm not sure why this behavior is observed with the debugger, functionality is not guaranteed if configuration is out of guidelines. To make it 100% working under all circumstances, 120MHz (or 60MHz) must be configured in described way.

Best regards,
Julián

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164 Views
Julián_AragónM
NXP TechSupport
NXP TechSupport

Hi @ManuSharma,

This is usually a clock settings issue. Please check AIPS_SLOW_CLK and HSE_CLK values. Also check DCM record regarding HSE_CLK_MODE_OPTION. With this, you know the ratio (either 1:2 or 1:4) that those clocks shall comply with.

You can test configurations from the S32K3 Reference Manual chapter 24.7.2 System clocking configurations and confirm if the issue persists.

Best regards,
Julián

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