How BCTU LIST items works?

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How BCTU LIST items works?

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MVR
Contributor III

Hello Everyone, 

I'm using S32K344 and S32K3 RTD AUTOSAR 4.4 2.0.1 D2207 in S32 Design Studio. I modified the example "Adc_Sar_Bctu_Ip_example..." to work with list and get 3 channels instead 1.

1) I would like to understand the BCTU LIST items. When I defined ADC0 channel P0, ADC0 channel P1, ADC1 channel P2, how must I configure these parts?

MVR_0-1671074252200.png

 

2) The loop for in BctuWatermarkNotif needs to loop 3 times? Or firstly 2 times (ADC0 P0 and P1) and after 1 time to get ADC1 P2?

3) I asked it because the conversion will not convert in the same time, because there are two channels in the same instance of ADC, correct?

4) Another question, if I want to configure ADC0 P0, ADC1 P0, how must I configure the list, according to this next figure? 

MVR_0-1671074769787.png

Thanks.

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

refer to attached modified code. It has also 9 items in the list. I added 3 GPIO pins to show when BCTU is triggered (PTA0), trigger notification is called (PTA1) and watermark notification is called (PTA2). Below is result when 3ADCs are triggered parallelly (ADC mask =7)

PetrS_1-1672848740715.png

For single ADC selected (ADCmask = 1) you got 

PetrS_2-1672848795752.png

BR, Petr

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) chapter 63.3.4 Multiple parallel conversions (MPC) of the RM explain how does channel list is taken when multiple ADCs are selected for a trigger. So if 2 ADCs are selected, in the channel list you should have 2, 4, 6 etc channel numbers defined

2) watermark specifies when notification will be called and how many reading from FIFO can be done. If you have watermark set to 3, notification is called when there are 4 entries in the FIFO and you can do 4 readings of FIFO.

3) within list you do not specify the ADC module, just a channel. Subsequent n elements in the channel list specifies set of selected ADC channels that perform their conversions in parallel for n selected ADC modules

4) yes, this should be correct. Last channel should be selected for each, I think.
ADC Target Mask should be 3, to select ADC0 and ADC1.

BR, Petr

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MVR
Contributor III

Hello @PetrS , thanks for attention.

1) Did you want to mean the section 62.12, right?

I'm a little confused yet, my understanding is:

The list of channels means the channels of each instance/module of ADC defined that will be read, after trigger. So, if we defined:

Channels: CH0 (p0) and CH1 (p1) in CL;

Modules/Instances: ADC0, ADC1 and ADC2 (Target Mask = 7).

it will read CH0 of all modules parallel and after CH1 of all modules parallel, correct?

The right configuration would be with this way:

MVR_0-1671111275625.png

Is it correct? If yes, my configuration in the last question (4) is wrong, because I could be only program the CH0 in the list, that it will read CH0 in ADC0 and ADC1 in parallel.

2)So basically, this watermark value will set according to number of channels that has in the list (if yes, the example that I shown above, should be 6)? Or according to number of channels that are in parallel (3 in example above)? Can you give an example with more than 1 channel and more than 1 module of ADC, please?

Thanks

 

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

1) yes, chapter 62.12 in RM rev4, 63.3.4 in RM rev5
if you select all 3 ADCs for a trigger, then 3 subsequent items in the list specifies channels to be converted in respective ADC modules, so first in ADC0, second in ADC1 and third in ADC2.
So for your example you should have another item in the list.

2) watermark need not to be set according items in the list, rather specifies after how many results stored in FIFO the DMA or interrupt request will be generated

BR, Petr

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MVR
Contributor III

Hello @PetrS ,

Good, now I understand.

But, when I was testing, I got some problem, take a look:

I programmed three instances of ADC (ADC0, ADC1 and ADC2) and 6 channels.  I want to get the all channels in one trigger:

MVR_2-1671485339171.png

MVR_3-1671485399246.png

If I set with this way, after the first step, the "Trigger Notification" is always called twice before calling the Watermark Notification.

If I set only 3 channels (removing the items 3, 4 and 5), and the macro BCTU_FIFO_WATERMARK as 3, it doesn't happen.

Is it wrong? Follow my code attached if you want to test.

Thanks,

MVR

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

I think it is correct. If 2 parallel conversions are set in the list, then CTU generates 2 ADC triggers so you get trigger notification called twice before watermark notification is called.

BR, Petr

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MVR
Contributor III

I'm sorry but It is a little confused yet, because I added 3 more channels in this code and I'm still having the same problem. In your guess, that should call 3 times the trigger interrupt before the watermark interrupt and it doesn't happen.

I added according to:

MVR_0-1671643438896.png

I Changed the "BCTU_FIFO_WATERMARK" macro from 6 to 9, changed the watermark value to 8 and defined the 3 channels on pinout configuration.

Thanks,

MVR

 

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

refer to attached modified code. It has also 9 items in the list. I added 3 GPIO pins to show when BCTU is triggered (PTA0), trigger notification is called (PTA1) and watermark notification is called (PTA2). Below is result when 3ADCs are triggered parallelly (ADC mask =7)

PetrS_1-1672848740715.png

For single ADC selected (ADCmask = 1) you got 

PetrS_2-1672848795752.png

BR, Petr

 

2,095 Views
MVR
Contributor III

Hello @PetrS 

Cool, as I was testing with breakpoint, the trigger notification was always called twice. When I remove the breakpoint, it works as per your explanation. Thanks very much!

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