What's the value of BOOT_CFG1 in QSPI boot with a Micron flash?

[chengpei]

Hi, 

I want to boot from flash of a Micron chip, MT25QU01GBBB on S32G274 on our board.

Now it is set to boot from serial RCON with an eeprom chip, it works fine when we boot from SD card with this 4 bytes:

I tried “00 00 00 00” and "00 10 00 00" to boot from flash, but it didn't work.

So, what's the valid value?

And I noticed that there are two phases of the QuadSPI configuration, is the initial one configurable? If yes, how can I configure it? And is the default setting works on MT25QU01GBBB? 

The datasheet of MT25QU01GBBB is attached.

Thank you.

[Daniel-Aguirre]

Hi,

The value "0x00000000" should be correct for booting from external NOR Flash. The default NOR Flash configuration for the S32G platform is designed for the Macronix embedded NOR Flash inside the NXP designs (MX25). If you require a different NOR Flash, you need to provide the reconfiguration that will be used under the 2nd stage.

More information is provided under the AN13563 (link: AN13563: S32G QuadSPI Deep Dive – Application note (nxp.com)) on regards of the reconfiguration parameters.

As for the 1st stage (QuadSPI initial configuration), the following is told under the S32G2 Reference Manual [Page 1347, S32G2 Reference Manual, Rev. 7, February 2023]:

"Configure the QuadSPI controller at a frequency of 40 MHz in 1-bit mode for Quad and Octal flash memories, and 8-bit mode for HyperFlash flash memories."

So, the only restriction is that the NOR Flash needs to be configure at the start to use 1-bit mode, it cannot be 4-bit/8-bit mode from the start.

Please, let us know.

[chengpei]

Hi,

The reconfiguration in my binary is empty:

According to the manual, it should continue the boot process with the initial configuration, run normally and just slower speed,

But the expected content was not present in my serial terminal:

So, I doubt that either there is something wrong with the Initial configuration or the value "0x00000000" maybe not correct.

[Daniel-Aguirre]

Hi,

Thanks for your feedback. There is a restriction under the QSPI interface, as said under the Reference Manual [Page 1347, S32G2 Reference Manual, Rev. 7, February 2023]:

"BootROM sets a timeout of 500ms when downloading the application image. User must ensure that the maximum image size can be downloaded within this time. The image size would depend on the configuration used."

Can you confirm if you are seeing your platform being reset? You should be able to define an example similar to the one shown under the "SW Enablement Guide", where the linker of the project is modified to use a smaller space of memory. We have used this example to run from NOR Flash without configuration.

Please, let us know.

[chengpei]

Hi,

I tested the SCK pad of QSPI with an oscilloscope on both boards(RDB2 & my board).

There should be no reset on my board, because the waveform didn't repeat(if reset, there should be cyclic every 500ms I think?).

And I also found that the frequencies of the SCK pads were different between the two board, 125MHz on RDB2 and 37MHz on my board.

SCK frequency on RDB2:

SCK frequency on My board:

And the Crystal(tested, 40MHz too.) circuit on my board seems the same with the one on RDB2:

So, with the same binary(without QSPI final configuration), why did the QSPI frequency being different?

As the manual said, maybe the PLL-DFS was not locked on my board, but how would this happened?

And are there any difference between these two chips(S32G275 on my board) which related on this topic?

And also, the reason for the flash failure on my board seems to be that it did not read out any data, because the waveform of the SCK pad only last for about 1.4ms while the waveform on RDB2 last for about 90ms(and the frequency is even higher)! 

SCK pad waveform of RDB2 last for about 90ms:

SCK pad waveform of My board last for about 1.4ms:

[Daniel-Aguirre]

Hi,

If the SCK frequency of the RDB2 board is being changed then a QSPI configuration is being sent to the Flash which was recognized, hence the change in frequency.

Are you sure that the code you are trying to load does not have any reconfiguration parameters?

Please, let us know.

[chengpei]

Hi,

I captured the QSPI data using a logic analyzer, and found that the BootROM reads only 256 bytes(1 frame) of the Application Bootloader which size is actually 5505112 bytes.

So, why the BootROM quit to read the rest of the Application after the first frame?

And how does the BootROM knows the size of each sub-image(Application, HSE etc.).

Notice there is only address information in the IVT header.

[Daniel-Aguirre]

Hi,

Is this from RDB2 or your board?

As for the IVT structure, the information should be provided under the Reference Manual [Chapter 30.4.1, S32G2 Reference Manual, Rev. 7, February 2023].

On how the BootROM knows how to read it, the following information is provided under the Reference Manual:

In which, BootROM passes the control to the respective code once it identifies the boot option.

Please, let us know.

[chengpei]

Hi,

The S32G2 BootRom does not support Micron MT25QU01GBBB?

In final qspi configuration phase, the BootRom try to send 0x72(Write Configuration Register) command to configure the flash chip, but 0x72 is not defined in MT25QU01GBBB.

0x72 is defined as the "write configuration register" in Macronic MX25UM51245G, which is the flash chip on RDB2.

Please help to confirm this, thank you.

[Daniel-Aguirre]

Hi,

S32G does not support additional NOR Flash from the default configuration. You are required to provide the reconfiguration parameters.

Please, let us know.