Anyone can explain the booting process ?
Can anyone look into below statement and correct if my understanding is wrong ?
Initially we need to select the Boot Mode using RCON or Fuse Configuration .
It will decide the location of IVT from where the Boot Manager is to be loaded.
If it's QSPI Load(Loading from NORFLASH) we need to place IVT at 0th Address, If it's any MMC device it should be at offset 0x1000.
The BootROM is the first sw that run after any reset.
It is placed in Internal ROM and is executed by M7 Core.
BootROM will load the IVT to SRAM (I need clarification of this) also since it contain location of the Bootmanager(BM) for M7 Core it will load that BM to SARM and run it from SRAM.
This BM will help in the peripheral /clock initializations. Later BM of M7 will help to Copy the BM of A53 from NORFlash or EMMC devices to SRAM and run from SRAM.
Later this will help to Copy the Customer Application or Linux to SRAM or DDR and will pass control to the Application .
Then Application began execution . After a Power ON Reset , the control directly comes to application only.
Please correct me if I'm wrong regarding the about flow.
NXP documents wasn't giving me a clear picture regarding the same .
(mainly regarding
> where the IVT will be copied by BootROM ? without peripheral init. how the copy of the to external memory take place (since SRAM is external for S32G2) ?
> Will BootManager for M7 will copy to SRAM by BootROM only ?
>Will peripheral init. clock init take place with the help of BM only?
> After Power on reset where the control will go if the program is currently running in application ? Should it follow the boot process again ? )
