PVR5510AMDAHES : Standby and debug mode operation

[pradeepprabhu]

Hi NXP Team,

Could you please clarify below queries about PVR5510AMDAHES PMIC part,

Please find the attached PVR5510AMDAHES schematics implemented in custom design.

1. It is given in the datasheet that when VDD_OTP is applied, PMIC will be pushed to debug mode and all regulator outputs are disabled.

But in the EVM schematics it is suggested to enable VDD_OTP always (J184 jumper connected by default). In this case PMIC is always in debug mode & no regulators are enabled, right?

Note: Above circuit is giving short duration pulse of 7.5V. Not continuous 7.5V to VDD_OTP pin.  

1. For the production, we are planning to use pre-programmed PMIC’s. hence we don’t need debug mode option in the design.

In this case, can we connect VDDOTP pin directly to ground and expect all the regulators output is enabled with proper power ON sequence?

1. In the current design, FS0B is not releasing even after all the regulators outputs are stable. but J184 (EVM) or R1342 (custom design) is mounted which is not the case as per query #1.

1. If R1342 is not mounted in custom design, PMIC RESET pin is continuously toggling making all regulators output are unstable.

Kindly go through the above queries and clarify the design requirement for PMIC in Standby mode operation?

Regards,

Pradeep

[CindyWen]

Hello Pradeep

It is my pleasure to help.

 Q1: It is given in the datasheet that when VDD_OTP is applied, PMIC will be pushed to debug mode and all regulator outputs are disabled.

But in the EVM schematics it is suggested to enable VDD_OTP always (J184 jumper connected by default). In this case PMIC is always in debug mode & no regulators are enabled, right?

Note: Above circuit is giving short duration pulse of 7.5V. Not continuous 7.5V to VDD_OTP pin.  

A1: When 7.5V is applied to VDDOTP, all the regulator output are disabled .  

When  VDDOTP level change to 0V from 7.5V, VR5510 is powered on in debug mode. All the regulators are on after that .

Please refer to the 8.12 Entering Debug mode using the VDDOTP   pin-  step4   in datasheet . 

Q2 : For the production, we are planning to use pre-programmed PMIC’s. hence we don’t need debug mode option in the design.

In this case, can we connect VDDOTP pin directly to ground and expect all the regulators output is enabled with proper power ON sequence?

 A2:  VR5510 need watchdog refresh when power on in normal mode.  And it do not need watchdog refresh when it power on in DBG mode which  allows the software driver debugging.

J184 can be disconnected, and the VR5510 can be powered on in normal mode (VDDOTP keeps 0V) when the software driver is ready in processor. 

Q3: In the current design, FS0B is not releasing even after all the regulators outputs are stable. but J184 (EVM) or R1342 (custom design) is mounted which is not the case as per query #1.

 A3: FS0B cannot be released when VR5510 is power on in debug mode.  Customer can refer to 8.15 Debug flow charts   description  in datasheet to release FS0B.

Q4: If R1342 is not mounted in custom design, PMIC RESET pin is continuously toggling making all regulators output are unstable.

 A4: VR5510 need watchdog refresh from processors in normal mode . Customer need to debug the software driver first  and make sure the VR5510 is correctly driven by processor. 

I didn't see customer design , Could you share it?

Any other questions , Please feel free to contact me . 

For PMIC questions , you can to to this community to ask.  Thanks

Power Management - NXP Community 

Brs

Cindy

[st_ra]

J184 can be disconnected, and the VR5510 can be powered on in normal mode (VDDOTP keeps 0V) when the software driver is ready in processor.

How do you do this? Because even if application which refreshes watchdog is in e.g. NOR FLASH, it does not have enough time to load and start to refresh it, PMIC will resete the board before that and cycle repeats. Not to mention if bootloader is used than it takes even longer to load application.

[CindyWen]

Hello  st_ra

 I am application engineer supporting VR5510.

Please refer to 8.6 Functional state diagram in VR5510 datasheet. After PGOOD/RSTB release, VR5510 enters into INIT_FS state and open a time window . This window can be configured to typical 1s (Max 67s) by VR5510 OTP. The first WD need to be refreshed before the window time out.

This first WD refresh will close the INIT_FS state and window WD is triggered after that.

Brs

Cindy

[pradeepprabhu]

Any updates