IPCF or XRDC with SEMA42

[Markus_Schroeder]

We are building a complex application on the S32G274A supporting several combinations of cores.
At least one of the A53 cores will run Linux.
At least one of the M7 cores will run FreeRTOS.

We need a good approach for communication between different cores.

The S32G2RM describes different types of hardware support for communication between different cores, for instance:

- Messaging Unit (MU), chapter 62
- Semaphores2(SEMA42), chapter 17
- Extended Resource Domain Controller (XRDC), chapter 15
- NoC Subsystem, chapter 6 (probably not relevant, since it might only be hardware based)
- Ncore, chapter 7 (probably not relevant, since it might only be hardware based)

There is also the Inter-Platform Communication Framework (IPCF)
see: https://www.nxp.com/design/automotive-software-and-tools/inter-platform-communication-framework-ipcf... 

This framework seems to be a good base.
But here is my question:

Does this framework use any of the above hardware supports for inter core communication?
When looking at the code, it seems to only rely on interrupts and static memory configuration, as well as using the ARM MPU for memory protection.
I see the advantage of being platform independent, but then are the above hardware features not an improvement?

Our first goal is to have a fast (high bandwidth) Ethernet-like interface between one A53 core and one M7 core.

Should we build this upon the IPCF or should we better use the hardware capability?

[Daniel-Aguirre]

Hi,

The framework's example works mainly with the "Miscellaneous System Control Module". There is a specific "Core-to-core" MSI that sends an interrupt from one core to another on the system (for A53, the interrupt goes directly to the GIC).

As for HW modules used on the IPCF, there is no explicit mention about them. Even if we look into the peripherals declared on the IPCF examples, no MU/SEMA42 elements are declared.

Given that the IPCF (theoretically) should only be limited by the specified read/write latency to the shared memory, should have high-bandwidth.

As for an ethernet-like feature inside the platform, we cannot find something explicit on the documentation. You could create a loop with your ethernet interfaces to communicate from one core to another, as you could do it with another communication interface like CAN, UART, SPI, etc...

In summary, IPCF has been the main implementation regarding core-to-core communication on what S32G has to offer.

On the other hand, XRDC is not defined as a HW communication interface between cores, but the module is defined as "focuses on how to
implement domain assignment for bus masters, and domain access control for memory regions and slave peripherals" [AN13024].

Please, let us know if this information was helpful or not.

[Markus_Schroeder]

Thank you for the answer.
Since this IPCF seems to have already some kind of implementation also on the Linux side,
this might be the better way to go. Even tough, it seems that it does not use any advantage of
the hardware, except interrupts.

The SEMA42 module and the XRDC module seem to be useful for a shared memory communication between cores.
See the example provided under "S32 RTD AUTOSAR 4.4 3.0.2 HF01 D2204 Example Projects" in
"Rm Examples" called "Xrdc_Ip_Example_integrated_with_Semaphore_S32G274A_M7".

For the IPCF, I have a further question:

There is a pdf on the following page:
https://community.nxp.com/t5/Connects-Training-Material/Abstracting-Inter-Platform-Communication-in-...

On page 14 there is an overview of the architecture. It seems, that there is a "Virtual ETH" part of the IPCF Framework.
This looks exactly like what we need.
The version of the IPCF, which I downloaded (SW32G_IPCF_4.6.0_D2205) does not have any Ethernet API.

Is this a feature planned in the future?
Is this meant to be implemented by the customer/me?
Is there a newer version of IPCF containing this "Virtual ETH" layer?

Best regards,
Markus

[Daniel-Aguirre]

Hi,

It does seem that the link you have provided is not related to S32G platform. What it is available on the IPCF on S32G is the diagram below (link: Inter-Platform Communication Framework (IPCF) - Product Brief (nxp.com)

Which does not have the virtual ETH you are mentioning. We do apologize.

As if there is plan on adding this, we do not have information about it. We may recommend sending this specific inquiry to your local NXP representative/FAE, given they could have the access to a roadmap. Still, for what we can see, there is no plan on doing it.

Please, let us know.