I used Flexio to simulate I2S communication，use SDK example.the SDK example offered a demo for flexio i2s,include 4 pins(SCK,WS,TX,RX),it's a three wires i2s protocol，but now we need a four wires i2s protocol（MCLK，SCK，WS，TX,no need rx），so we need to patch a master clock（MCLK,PTE10） for four wires I2S .Our flexio peripheral clock is 48MHz（or can configure it to 112MHz）.we all known,audio signals often require a clock that is not an integer multiple,MCLK = （128,196,256...）* Fs, Fs may equals 22.05kHz,26.8kHz,28.2kHz,44.1kHz...).If we divide from Flexio timer,MCLK will not produce the frequency I need，because it only has integer multiples frequency.So Is there any other way to get the any frequency I need?In addition,how to ensure that the phase of MCLK we generated is the same as SCK?Looking forward to your reply。Many thanks
Please take a look at this application note:
The example there uses MCLK.
But as you mentioned, it is difficult to get the standard frequency from the 48MHz clock.
The application note recommends using special crystals.