mc9s12xd64 irq set to lowest priority

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mc9s12xd64 irq set to lowest priority

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barc
Contributor I

Workaround is:

Where using IRQ in edge-sensitive mode then configure the interrupt 
priority levels of all interrupts being used to ensure that the IRQ 
request always has the lowest priority. 

My Question: How do I lower IRQ interrupt priority? Seems there is only access to 8 vectors to change their priority. All int's are priority 1 out of reset by default. I use several interrupts and would have to raise their priority while leaving IRQ priority at 1 so IRQ is the lowest.

Anyone know how to accomplish this?


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kef2
Senior Contributor V

Like Interrupt module Introduction states, you can change priority of every I-bit interrupt, not just 8. To save registers space, you have just 8 INT_CFDATAn registers, but also INT_CFADDR, which maps different INT_CFDATA regs to address space. CW project wizard suggests you using this macro to change priority levels or redirect interrupts to XGATE:

#define ROUTE_INTERRUPT(vec_adr, cfdata)                \

  INT_CFADDR= (vec_adr) & 0xF0;                         \

  INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

where vec_adr is CPU12X interrupt vector address, cfdata - desired priority level (see INT_CFDATA description).

(I never user IRQ pin in edge mode. I find it somewhat fuzzy to use edge interrupt without corresponding interrupt flag. Port interrupts or timer interrupts IMO are better choice for external edge interrupts.)

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barc
Contributor I

Appreciate your reply! I am thinking the same. I've got a spare port p pin, so I think I will use that instead of the IRQ pin. Too complex to deal with priority change.

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kef2
Senior Contributor V

S12X priority levels are very clear, rock solid and useful compared to IRQ pin usage in edge triggered mode. If I knew what makes IRQ latch cleared, maybe I would change my opinion. Documentation says it is "cleared only upon a reset or servicing of the IRQ interrupt". Fine, but at wich point of servicing IRQ interrupt? On entry, on exit, in the middle? What exactly causes it? Some wire of interrupt controller? If so, then is there some timing diagram? This is not clear since old HC12, where this falling edge feature was introduced. And I'm still curious about it. You may ask me why I didn't ask support for this. Well, mea culpa, it was simplier to avoid using it...

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