Hi all,
I finally have CodeWarrior up and running with my obscure printer port... I am evaluating the 56F8013EVM for a home project I hope to turn into a product, and I am seemingly having some difficulties getting any performace out of the core.
I have set up a processor expert project only turing on the bare essentials; The Cpu where I have the PLL clock set at 32MHz and using the On-chip relaxation oscillator, and two of the LEDs since I am using the EVM board for this test.
I then simply call LED1_Toggle() in the for(;
block of code in the main User Modules secion and observe the output on the pin.
I was hoping if the core was running at 32MHz to see an output between 4-8MHz, maybe faster. Instead I see an output of 1.6MHz on a bare bones project, and a whopping 276kHz with the A/D module turned on in continuous mode.
First off, with the JTAG cable attached, does it slow things down when running?
I get no PLL error interrupts, however when I poll the locked flag of the PLLSR, it always says unlocked, though I am unsure how this could pass the initialization stage if so as the CPU initialization wont exit unless a lock ocurs.
Currently this project is pretty darned slim, so I cannot imagine much being wrong at this point, other than the device's PLL not cooperating or ProcessorExpert generating a crummy piece of code someplace which causes the PLL to unlock.
Thanks for any insight if anyone has run into this one before.
And quickly: Can I expect to be able to get a 32kHz sample rate on two channels at once? Even better, can I expect 32kHz sample rate staggered on four? I have been unable to confirm this on the demo board thanks to this clocking issue. The datasheet says so.
-Mark
I finally have CodeWarrior up and running with my obscure printer port... I am evaluating the 56F8013EVM for a home project I hope to turn into a product, and I am seemingly having some difficulties getting any performace out of the core.
I have set up a processor expert project only turing on the bare essentials; The Cpu where I have the PLL clock set at 32MHz and using the On-chip relaxation oscillator, and two of the LEDs since I am using the EVM board for this test.
I then simply call LED1_Toggle() in the for(;
block of code in the main User Modules secion and observe the output on the pin.I was hoping if the core was running at 32MHz to see an output between 4-8MHz, maybe faster. Instead I see an output of 1.6MHz on a bare bones project, and a whopping 276kHz with the A/D module turned on in continuous mode.
First off, with the JTAG cable attached, does it slow things down when running?
I get no PLL error interrupts, however when I poll the locked flag of the PLLSR, it always says unlocked, though I am unsure how this could pass the initialization stage if so as the CPU initialization wont exit unless a lock ocurs.
Currently this project is pretty darned slim, so I cannot imagine much being wrong at this point, other than the device's PLL not cooperating or ProcessorExpert generating a crummy piece of code someplace which causes the PLL to unlock.
Thanks for any insight if anyone has run into this one before.
And quickly: Can I expect to be able to get a 32kHz sample rate on two channels at once? Even better, can I expect 32kHz sample rate staggered on four? I have been unable to confirm this on the demo board thanks to this clocking issue. The datasheet says so.
-Mark
