Enabling PLL to get a different SCI baud rate

[cerebral_mamba]

Hi,

My crystal is 20MHz and with a Bus Clock of 10MHz (osc/2), I can communicate with SCI0 at 153600 baud fine. But now I want to change it to 115200 baud and since 10MHz does not allow that (nearest integer SCIBD value results in a lot of error), I thought of using the PLL and get the desired bus clock freq.

The problem is that the PLL does not seam to be doing anything. I have re-verified the hardware design and XFC filters have been designed properly.

Below is my code (Codewarrior 4.5), please tell me if I am missing something and possibly how to know for sure that the PLL is being enabled.

 SYNR = 5;                           //to get PLL as 40MHz from a 20MHz OSC
 REFDV_REFDV = 5;           //to get PLL as 40MHz from a 20MHz OSC
 CLKSEL_PLLSEL = 1;
 PLLCTL_AUTO = 1;
 PLLCTL_PLLON = 1;
 
I have verified that CRGFLG_LOCK bit gets set to 1 indicating that PLL is within tolerable range.

1. Is there anything else I need to do inorder to get the PLL to work?
2. Will the changed PLL clock freq. change the input clock freq. to the SCI module also?

Thanks a million
Sujith

[Lundin]

It sounds strange since you are certain that the filter is ok. You aren't telling which MCU you are using, assuming HCS12.

On HCS12 you must use the Pierce oscillator to be able to reach 40MHz bus. Are you using this oscillator?

What does the oscillator clock look like? Might not be accurate to measure unless you have special probes for the oscilloscope, but even without one, you will get the rough picture. Is it still running at 20MHz? Is it stable, ie has the PLL locked?

The register CLKSEL is "write-once" in normal single-chip mode. Make sure no other part of the code is writing to this register before you do.

If you enable SCMIE in CRGINT, do you get self-clock mode interrupts? Note that self-clock mode is enabled by default out-of-reset, just not the interrupts.

1) No.
2) The PLL will indeed change the clock input to the SCI and to every other peripheral since the busclock is derived from the PLL (PLL clock / 2).