About the I_D limitation of S12XHZ

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About the I_D limitation of S12XHZ

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ikkishingu
Contributor II

Hello,

 

There is the spec on MC9S12XHZ512 data Sheet Rev 1.06
as below,
--
A.1.5 Absolute Maximum Ratings
Instantaneous maximum current
Single pin limit for Port U, V and W
I_D min -55mA  max  +55mA
--
Then is it OK so long as I_D(port U,V&W) doesn't become over +55mA/-55mA?
Or is there any limiation?
temperature, constant current, current sum of multiple pin..

 

Best Regards,
Ikki

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lama
NXP TechSupport
NXP TechSupport

On the basis of our communication I would like to add some data which can be interesting during design.

Each Vdd and Vss pin has current limitation which should not be exceeded.

for example:

                  XDP[mA] XHZ[mA] S12G[mA] XEP[mA]

VDDX1(2,3)  50          100        60      100            

VSSX1(2,3)   50          100        60      100    

VDDR           40             -           -         -               (in the case of XHZ, XEP, G it does not supply GPIO pins)

VSSR            40             -           -         -               (in the case of XHZ, XEP, G it does not supply GPIO pins)

VDDM1,2,3    -            80           -         -                  

VSSM1,2,3     -            80           -         -

Consideration:

Let's suppose current limitation at Vdd or Vss pin +/ –100 mA and let’s suppose only one pair of VDDx/VSSx pins.

The current we can take through the power supply ring on the silicon itself is surprisingly low (+/-100mA) - because of electromigration limit. It is a limit per Vddx and Vssx rail individually. It means you can drive a few loads to log.1 and few loads to log.0 in order to increase number of loads.

(Let’s suppose 25x4mA external devices switched to log.0 and 25x4mA diodes switched to log.1 (supplied directly from MCU pins). In this case 100mA flows from Vddx through diodes to gnd. Next 100mA flows from external source through diodes to VSSX. In this case we are able to drive 200mA but we are not allowed to add any load. If higher current than 100mA flows through VDDX or VSSX it can destroy this pin because of current density.)

Let's say an automotive dashboard manufacturer wants to drive 30 LEDs with the micro (driven to log. 1 – Vddx supplies diodes), 4mA each. Let’s say the MCU has only one pair of VDDX/VSSX supply pins. That is 120mA of current, 0.4V drop across the I/O structure => 48mW power dissipation. That will take the device temperature up approximately 2degC (at 43K/W). That is not too much in terms of temperature rise, but the current is higher than single pin (100mA) limit!

Best regards,

Ladislav

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lama
NXP TechSupport
NXP TechSupport

On the basis of our communication I would like to add some data which can be interesting during design.

Each Vdd and Vss pin has current limitation which should not be exceeded.

for example:

                  XDP[mA] XHZ[mA] S12G[mA] XEP[mA]

VDDX1(2,3)  50          100        60      100            

VSSX1(2,3)   50          100        60      100    

VDDR           40             -           -         -               (in the case of XHZ, XEP, G it does not supply GPIO pins)

VSSR            40             -           -         -               (in the case of XHZ, XEP, G it does not supply GPIO pins)

VDDM1,2,3    -            80           -         -                  

VSSM1,2,3     -            80           -         -

Consideration:

Let's suppose current limitation at Vdd or Vss pin +/ –100 mA and let’s suppose only one pair of VDDx/VSSx pins.

The current we can take through the power supply ring on the silicon itself is surprisingly low (+/-100mA) - because of electromigration limit. It is a limit per Vddx and Vssx rail individually. It means you can drive a few loads to log.1 and few loads to log.0 in order to increase number of loads.

(Let’s suppose 25x4mA external devices switched to log.0 and 25x4mA diodes switched to log.1 (supplied directly from MCU pins). In this case 100mA flows from Vddx through diodes to gnd. Next 100mA flows from external source through diodes to VSSX. In this case we are able to drive 200mA but we are not allowed to add any load. If higher current than 100mA flows through VDDX or VSSX it can destroy this pin because of current density.)

Let's say an automotive dashboard manufacturer wants to drive 30 LEDs with the micro (driven to log. 1 – Vddx supplies diodes), 4mA each. Let’s say the MCU has only one pair of VDDX/VSSX supply pins. That is 120mA of current, 0.4V drop across the I/O structure => 48mW power dissipation. That will take the device temperature up approximately 2degC (at 43K/W). That is not too much in terms of temperature rise, but the current is higher than single pin (100mA) limit!

Best regards,

Ladislav

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ikkishingu
Contributor II

Dear lama,

Thank you for your info!!

Ikki

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lama
NXP TechSupport
NXP TechSupport

The data sheet states: Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.

The 55 mA limit is actually the maximum ratings, meaning that anything beyond that limit could damage, so a lower margin should be used. There is also a limit to what the ports (the sum of all the pins) can supply. Another limit is power dissipation.

Entire design should be done for Table A-6. I/O Characteristics, specs 5 and 6 and defined logic levels for used logic:

Output high voltage min (output mode)             

Partial drive: IOH = –2 mA                   VDD5 – 0.8V

Full drive: IOH = –10 mA2                    VDD5 – 0.8V

Port U, V, W: IOH = –20 mA 3               VDD5 – 0.32V

Output low voltage max (output mode)              

Partial drive: IOL = +2 mA                    0.8V

Full drive: IOL = +10 mA                      0.8V

Port U, V, W: IOH = +20 mA  0.32V

One VDDX/VSSX supply pin is able to be loaded by 40mA/40mA. Over this value electromigration can damage the pin. On VDDM1,2,3 since they are made to drive huge loads the limit is significantly higher. For one VDDM pin it is 80mA/80mA per VDDM/VSSM.

Best Regards, Ladislav

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