We are currently bringing up LX2160A SoC and while running the DDR "Centering the clock" validation, we hit into issue with only some of the DDR4 chips. We are using discrete DDR4 memory running at DDR Data Rate 1600MT/s (64-bit bus mode), CS0 enabled. Same error happens for our DDR_mc2 controller. Any idea/suggestion how to further debug the problem with QorIQ?
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Iterration: 1
phy_vref: 0x40
dram_vref: 0xa
mr6: 0x40a
Start ddr_phy_init...
[1] PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x1001 ****
[1] PMU10: PHY TOTALS - NUM_DBYTES 9 NUM_NIBBLES 18 NUM_ANIBS 12
[1] PMU10: CS=0x01, TSTAGES=0x031F, HDTOUT=5, 2T=0, MMISC=0 AddrMirror=10 DRAMFreq=1600MT DramType=2
[1] PMU10: Pstate0 MRS MR0=0x0614 MR1=0x0101 MR2=0x0000 MR3=0x0000 MR4=0x0000 MR5=0x0701 MR6=0x040A
[1] End of initialization
[1] PMU5: CS0 <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)
[1] PMU5: ID=0 -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --
[1] PMU5: [0]:0x 1df 1dd 1dd 1dd 7e8 7e8 7e8 7e8 7e8 0
[1] PMU5: [1]:0x 1df 1df 201 1df 7e8 7e8 7e8 7e8 7e8 0
[1] PMU5: ID=1 -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --
[1] PMU5: [0]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [1]:0x 10 10 10 10 10 10 10 10 10 0
[1] End of read enable training
[1] PMU5: CS0 <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)
[1] PMU5: ID=0 -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --
[1] PMU5: [0]:0x 43 47 9f 43 399 0 399 399 399 0
[1] PMU5: [1]:0x 43 47 9f 43 399 0 399 399 399 0
[1] PMU5: ID=1 -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --
[1] PMU5: [0]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [1]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [2]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [3]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [4]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [5]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [6]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [7]:0x 10 10 10 10 10 10 10 10 10 0
[1] PMU5: [8]:0x 10 10 10 10 10 10 10 10 10 0
[1] End of fine write leveling
[1] PMU: Error: dbyte 4 lane 0's per-lane vrefDAC's had no passing region
[1] PMU: ***** Assertion Error - terminating *****
[1] Firmware has failed (firmware completed)
Phase 0 (End of initialization) completed!
Phase 1 (End of read enable training) completed!
Phase 2 (End of fine write leveling) completed!
Phase 3 (End of read dq deskew training) failed!
Phase 4 (End of MPR read delay center optimization) failed!
Phase 5 (End of Write leveling coarse delay) failed!
Phase 6 (End of write delay center optimization) failed!
Phase 7 (End of read delay center optimization) failed!
Phase 8 (End of max read latency training) failed!
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