Exception Levels in T2080 architecture to read system ticks

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Exception Levels in T2080 architecture to read system ticks

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Contributor I

I am using both T2080 (PPC) and LS1046A (ARMv8) in my system. I am trying to come up with a common approach to read the system timer using the timer ticks. 

In LS1046A ARM processor, it is defined per the ARMv8 architecture where there are 4 exception levels namesly (EL0, EL1, EL2 and EL3) for accessing timer value by different SW levels.

Is there any similar concept in T2080 processor. If so, where could i get these information.

With the information, i need to identify a way to read the system ticks.

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NXP TechSupport
NXP TechSupport

Are you asking about PPC exception levels?

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Contributor I

Yes. I am looking at PPC exception levels. 

Also i am looking at accessing the System ticks (Timer counter ticks for PPC).

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NXP TechSupport
NXP TechSupport

The T2080 chip uses E6500 core that has the following privilege levels:

1-  user level

2-  Guest Supervisor

3-   Hypervisor

 

There are four categories of interrupts, described as follows:

  • Standard interrupts
  • Critical interrupts
  • Debug interrupts
  • Machine check interrupts

 

please refer to Asynchronous Exception Priorities table in the E6500 reference manual.

with regards to your question about timer tics , I think you would be looking for Fixed Interval Timer, FIT, or  Time Base Register ,TB, or watch dog timers. You can find more description about this in the timer register sections of the E6500 reference manual.

 

Please notice that the time base counters can be clocked by RTC signal or some core clock derivative  as will as the timer registers available in the MPIC which is another source of interrupt for sw to be aware of timing.

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Contributor I

Thank you. This helps.

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