eTSECs TSECn_GTX_CLK not working

[kwangyongyang]

Hi. 

I am using the MPC8572E processor.

MPC8572 eTSECs is connected Marvell 88E1111 single PHY. 

The mode between MAC and PHY is RGMII.

ethernet link partner support 1Gbps.

at room temperature.... ethernet working fine. 

but, at low temperature ... ethernet link is not establishing.

strictly speaking, repeat link up and down infinitely.

In this state, Transmit clock(TSECn_GTX_CLK) is not working, drive low.

What causes the TSECn_GTX_CLK not working ?

What registers are available for debugging?

Thank you for your help.

[alexander_yakov]

MPC8572 Reference Manual, Table 15-2 "eTSEC Signals" - states that "TSECn_GTX_CLK - This signal is driven low unless transmission is enabled". In other words, as long as your Marvell PHY cannot establish link with remote PHY, it cannot report link as established, so driver does not enable eTSEC controller, and TSECn_GTX_CLK is not oscillating because eTSEC is not enabled.

Have a great day,
Alexander

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[kwangyongyang]

Hi Alexander, thank you for your reply.

Ethernet is always connected to a PC that supports Gigabit Ethernet.

I am using windriver vxWorks OS on the MPC8572.

Additional findings...

1. I used a spot freeze spay to find out which part was the problem.

As a result, a problem occurs in which the PHY chip is in a low temperature state.

2. I found that the above problem is different depending on the vxWorks version.

In vxWorks 6.8, the problem occurs. but, The problem does not occur in vxWorks 6.9.

So I looked for differences between vxWorks 6.8 and 6.9 about etsec.

As a result, problems have occur or not occur according to the following differences.

The following two lines have been added since upgrading from 6.8 to 6.9.

following code re-configure the etsec interface mode.

/* Set an initial interface mode.
 * This may not be correct, but we have to choose one of the valid selections (byte or nibble mode).

 * Choosing an invalid selection might prevent us from establishing a link.
 */

CSR_CLRBIT_4(pDev, ETSEC_MACCFG2, ETSEC_MACCFG2_IF_MODE);
CSR_SETBIT_4(pDev, ETSEC_MACCFG2, ETSEC_IFMODE_MII);

As soon as the above code is executed, the Ethernet link is up and TSECn_GTX_CLK is working. 

So ..Check register values before and after added code.

logMsg("1.ETSEC_MACCFG2 : 0x%x \n", CSR_READ_4(pDev, ETSEC_MACCFG2));
CSR_CLRBIT_4(pDev, ETSEC_MACCFG2, ETSEC_MACCFG2_IF_MODE);
logMsg("2.ETSEC_MACCFG2 : 0x%x \n", CSR_READ_4(pDev, ETSEC_MACCFG2));
CSR_SETBIT_4(pDev, ETSEC_MACCFG2, ETSEC_IFMODE_MII);
logMsg("3.ETSEC_MACCFG2 : 0x%x \n", CSR_READ_4(pDev, ETSEC_MACCFG2));

result is as follows : 

1.ETSEC_MACCFG2 : 0x7115
2.ETSEC_MACCFG2 : 0x7015
3.ETSEC_MACCFG2 : 0x7115

As the above results, register value is same before and after new code execution.

I do not know why link up when re-configure interface mode.

Thank you for your help.

[alexander_yakov]

I can not comment about the reason, why you your software changes I/F mode field from valid value "01" to the value "00", which is marked as "Reserved" in our documentation (MPC8572E Reference Manual, Rev 2, Table 15-43). As per my understanding, this is just a mistake. Please address this question to vxWorks software vendor.