csb_clk maximum frequency of MPC8349E-667Mhz for DDR2 data rate of 400Mhz

[mallik]

Hi,

This is my first post.

we are in the concept phase of our design.

we want to use MPC8349E-667Mhz and interface 8+1 , 8 bit DDR2 400Mhz chips to it.

When i see clocking options for the IC, i need one clarification.

We need to use 400Mhz data rate DDR2 SDRAM. So, 200Mhz is the DDR Clock frequency. from MPC8349EAEC Rev 13 datasheet, ddr_clk = csb_clk*(1+RCWL[DDRCM]), ddr_clk is the controller inside module clock, clock which driven onto the actual interface is ddr_clk/2, so, for our requirement ddr_clk = 400Mhz, and RCWL[DDRCM] can be either 0 or 1. From Table 57  csb_clk varies from 100-333 for 667 Mhz core clock part. So, csb_clk can't be 400Mhz( as it exceeds the spec).

So, csb_clk can be 200Mhz and RCWL[DDRCM]=1

But, MPC8349EA reference Manual Table 4-8 says "The 2:1 mode is useful mostly when for a 32-bit data bus memory device."

Is that mean whether i can't use RCWL[DDRCM]=1 for 64-bit interface of DDR2-SDRAM 400Mhz for MPC8349EC-667Mhz Part

[Bulat]

Yes, your understanding is correct. DDR can be used at 400MHz if interface is 32-bit wide, CSB frequency would be 200MHz in this case.

[mallik]

Just want to confirm one more time

I have doubt, because they have used word "mostly".

So, then MPC8349EA -667 part will not support DDR2- 400Mhz. So, i need to go for lower speed memories next i want to go is 333Mhz.

As csb_clk max freq is 333Mhz.

I have 2 choices,

1. CLKIN =66.67Mhz,  CFG_CLKIN_DIV = 0, SPMF=  5:1 and DDRCM = 0 ===>csb_clk= 333 Mhz (By assuming DDRCM= 0 or 1, LBIUCM= 0 or 1 Max SPMF value = 4)

2. CLKIN =33.33Mhz,  CFG_CLKIN_DIV = 0, SPMF =10:1 and DDRCM = 0 ==> csb_clk = 333 Mhz( when DDRCM =0 and LBIUCM =0 SPMF max =16)

any other considerations for selecting CLKIN oscillator.

Edit:

There is an update from freescale saying that

"

This RCWL[DDRCM]=1 can be used for 64-bit DDR SDRAM interface - please refer to the MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Table 66. Part Numbering Nomenclature, note 4:

"ALF marked parts support DDR1 data rate up to 333 MHz (at 333 MHz CSB as the 'F' marking implies) and DDR2 data rate up to 400 MHz (at 200 MHz CSB)." "

[Bulat]

You should understand that data rate on the internal bus is defined by CSB frequency. Even if you run DDR at 2x CSB, the data rate within the processor is still defined by CSB. In that sense 2x DDR frequency is useful for 32-bit memory because data rate will be the same as on CSB. For example, if CSB frequency is 333MHz, its data rate 333MHz * 8Bytes = 2666 MByte/s. For 32-bit DDR at 666MHz data rate, it will be the same: 666MHz * 4Bytes = 2666 MByte/s. Or in other words, 2x DDR frequency for 64-bit memory does not provide any advantage in terms of performance, just increases power consumption of the DDR.

[mallik]

So, For DDR2 400Mhz data rate with 64-bit datawidth, 400*8B = 3200MBytes/transfer, but because CSB_CLK is 200Mhz, internal data transfer speed wil be 200*8B = 1600MB/transfer.

So, cases where CSB_CLK and DDR_CLK are equal will be suited for 64-bit interface