P2041 TBI Block Wrong Link Status

[enisaslan]

Hello,

I am working with custom P2041 board. There are two SGMII PHY but there is not MDIO bus for this PHYs (as hardware). In shortly, I can't configure to PHYs with MDIO Bus. But I'm using TBI block for the PHY link and speed status information. But reading wrong link status. First PHY RJ45 Cable Plugged and second PHY RJ45 cable unplugged. In this situation link status bit is SET and remote fault bit is SET in the TBI_SR register for first PHY. And Link status bit is SET for the second PHY too, even if RJ45 cable unplugged.

I found this errata:
https://www.digikey.com/htmldatasheets/production/1613014/0/0/1/p2040-1-3041-4080-5020-40-errata.htm...

I am read BnGCRm1[REIDL] register and value: 0x00040080 for both first PHY and Second PHY.

REIDL Bit always is zero.

How can I read correct link status information?

Thanks.

Enis

[Chavira]

Thank you for contacting NXP Support!

If TBI SR[Link Status] = 0, the link is down. For affected systems, in addition to examining the TBI link status, examine the SerDes electrical idle state. The link is actually down if either the TBI link status is cleared or the SerDes lane receive electrical idle is detected. SerDes electrical idle detected is BnGCRm1[REIDL] = 1 for bank n, lane m.

Example pseudo-code:

[enisaslan]

Actually I want to read PHY to PHY link status through SGMII bus.(with TBI registers).

Is it possible to do this ?