MPC8544 DDR2 Calibration

[cchermesh]

We have a design based on MPC8544, using one chip-select DDR2 embedded memory.  Several projects use successfully this design, except one project that some of its cards are reporting memory test failed.

Checking the DDR controllers' registers, we find that ERR_DETECT[ACE]=1 (An automatic calibration error has been detected).

Please help regarding this issue.

Thanks.

[Hector_Villarruel]

Hello @cchermesh 

Hope this post finds you well,

The ERR_DETECT shows ACE error which can be set for 2 reasons:

1) Automatic CPO calibration was enabled by setting TIMING_CFG_2[CPO] to 11111 and an error was reported and also for write leveling calibration.

2) The training sequence that the controller follows at POR to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings. 

Have a great day.

BR,

Hector 

[cchermesh]

Hello Hector,

Thanks for the fast reply.

1) Our setting for TIMING_CFG_2[CPO] is 00110. It's not clear to me, what do you mean by "… and an error was reported and also for write leveling calibration."

2) Can you please suggest which other incorrect controller settings may most probably cause the calibration failure?

Note: Our settings for I/O driver impedance are:

            DDR_SDRAM_CFG[HSE]=1 (Half strength).

            DDRCDR=0x00000000.

Have a nice day.

Best Regards,

Chaim 

[Hector_Villarruel]

Hello @cchermesh 

We were reviewing this information with the team and here is the recommendation that we can give you:

After negation of HRESET perform an alternative DDR controller initialization sequence for
each utilized controller.

This clears the DRAM state machines and allows them to operate
properly. Before this sequence is implemented do not enable any DDR LAWBAR entries.
Details of alternative sequence are as follows:
NOTE the following DEBUG registers:
• DEBUG_2 offset is CCSRBAR + DDR_OFFSET + 0xf04
• DEBUG_3 offset is CCSRBAR + DDR_OFFSET + 0xf08
1. Configure DDR registers as is done in normal DDR configuration. Do not set
DDR_SDRAM_CFG[MEM_EN].
2. Set reserved bit EEBACR[3] at offset 0x1000.
3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT].
4. Before DDR_SDRAM_CFG[MEM_EN] is set, write D3[21] to disable data training.
5. Wait 200 μs (as described in the section “DDR SDRAM Initialization Sequence,” in the
applicable device reference manual)
6. Set DDR_SDRAM_CFG[MEM_EN].
7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware.
8. Clear D3[21] to re-enable training.
9. Set D2[21] to force the data training to run.
10. Poll on D2[21] until it is cleared by hardware.
After this step there are two options that can be followed if ECC is enabled before
continuing on to step 11 . If DDR ECC is not utilized enable the DDR LAWBARs and
continue to step 11 . Sub-Option 1 requires a calculated delay. Sub-Option 2 does not
require the delay, but it is not supported for applications with DDR interleaving enabled.

• Another alternative from this recommendation 1

a. Wait calculated delay
Required delay for 64-bit DDR2 can be calculated as follows:
Delay = 400 ms/Gbytes × max memory size
For 32-bit data buses, multiply this number by 2.
Example: assume 64-bit DDR2, memory size = 1 Gbyte
Delay = 400ms/Gbytes × 1 Gbyte = 400 ms
b. Set DDR_SDRAM_CFG_2[D_INIT]
c. Poll on DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware, then the
system can proceed.
d. Enable any DDR LAWBAR entries and proceed to step 11 .

• Another alternative from this recommendation 2

a. Enable any DDR LAWBAR entries.
b. Set ERR_DISABLE[MBED] and ERR_DISABLE[SBED] to disable SBE and MBE
detection.
c. Complete a 32-byte non-snoopable DMA transaction with the source and
destination address equal to the DDR initialization address which is either the
starting address of CS0_BNDS by default or programmed in DDR_INIT_ADDR.
d. After the DMA transaction has completed clear ERR_DISABLE[MBED] and
ERR_DISABLE[SBED] to enable SBE and MBE detection as desired for specific
applications.
11. Clear reserved bit EEBACR[3] at offset 0x1000.

Have a great day.

BR,

Hector V

[cchermesh]

Hello Hector,

Thanks again for your recommendation.

We performed your alternative DDR controller initialization sequence (no ECC option in our cards), on two cards with the memory test failed report ("bad cards") and on another two cards without this report ("good cards").

After running the sequence, still the "bad cards" failed and the "good cards" operate correctly.

Note: with the "bad cards", at step 10 in the sequence, D2[19] was set.

Can we please get description of the DEBUG_2 and DEBUG_3 registers?

Have you an additional recommendation?

Have a nice day.

Best Regards, Chaim

[cchermesh]

Hello Hector,

Thanks for your recommendation.

We are working on it (also busy with other projects). I'll inform you about our test results ASAP.

Have a nice day.

Best Regards, Chaim