Table of Contents Product Information on Freescale.com MPC8306 Product Summary Page MPC8306 Documentation MPC8306 Software and Tools MPC8306 Parametrics MPC8306 Training Frequently Asked Questions (FAQ) MPC8306/MPC8306S Clocking Specific FAQs MPC8306/MPC8306S Hardware Specifications/Reference Manual Specific FAQs MPC8306/MPC8306S QUICC Engine Specific FAQs Other Resources CodeWarrior for Power Architecture Processors Optimizing CodeWarrior on Power Architecture Tips for your brand new CodeWarrior TAP! (Power Architecture)

Is there any suggested approach to determining the tx/rx ring buffer sizes on the peripherals that interface to the UCC? How can I decide on the ring size? The bandwidth would be 45 Mbps. The MTU on the serial interface can range up to 16k Bytes. Even if MTU could be 16K bytes, the average frame could be much smaller. Find out the average frame size and pick up a buffer size that is bit larger than the average frame size. This usually creates a good balance of efficiency between processing time and memory usage. It is much more efficient in terms of processing time to process a frame of 16K in one BD/Buffer of 16K size than in 16 BDs/Buffers of 1K size. However, if all buffers are 16K size while 90% of the frames are 1K, most memory is wasted. Generally, the ring size should be equal to the number of BD’s required to accommodate the largest possible frame size + 4 extra BDs. However, over here the bandwidth is relatively high (45M) and could be quite bursty. Hence we would suggest starting with "TWO largest possible frame size + 4 extra BDs" P1016 Hardware spec says that the QUICC engine periodically polls its Rx/Tx rings and if a BD is not empty, checks the ownership flag and moves to the next step. How does the user application trigger/control the QE to start polling? For TX BD ring, (after configured) QE will periodically poll the ring and process the BD that is not empty and then move to next BD. When a BD is actually transmitted, a "transmission complete" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released. For RX BD ring, (after configured) QE will pre-fetch a BD and then process the BD when data is received. When a packet (frame) is received, a "received" event (and interrupt if enabled) will be generated, so the BD/Buffer can be released/processed. If no empty BD is available during the pre-fetch, an "out-of-BD" error will be reported. After MPC8306 QE reset, when cores enables transmitter but BD is not ready, what signal will be on the line - IDLE(0XFF) or flags(7E)? Can this signal be configured? Yes, it should be configured by GUMR[RTSM].

For MPC8541, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.

MPC8536 PCI controller can get clock from SYSCLK (synchronous) or from PCICLK (PCI asynchronous mode). If PCI is configured as PCI asynchronous mode, a valid clock must be provided on pin PCICLK, otherwise the processor will not boot up. Is this limit just due to PCI bus specs and if PCI is not used then MPC8536 PCI block can withstand 125MHz in synchronous mode? The PCI input clock frequency spec range is between 33 - 66MHz. IF the PCI interface is enabled, then this spec here will matter regardless whether you are running in synchronous or asynchronous mode. IF the PCI is disabled / un-used, it will not matter what input clock is being fed into this interface. Also, please refer to section 15.2 of the 8536 bring-up guide for termination details of the PCI pins including the PCI1_CLK pin when the interface is not being used. I am starting 8536 design making use of both SerDes serial interfaces: 1) SerDes1: PCI Express 1 (x4) (2.5 Gbps) → SerDes1 Lanes A-D; PCI Express 2 (x1) (2.5 Gbps) → SerDes1 Lanes E-F 2) SerDes2: SATA1 → SerDes2 Lane A. Each SerDes has its own reference clock. They will both run at 100MHz. Are there any phase requirements between these 2 clocks? There is no requirement on 8536 for any particular phase relationship between reference clock for Serdes 1 vs Serdes 2 because each serdes is completely independent.

MPC8535 Hardware spec states that either SDHC_CD, or SDHC_DAT3 can be used for card detection. Do you have to set the bit PROCTL[D3CD] specifically, if you want to use the DAT[3] method? This, plus adding the pull-down? PROCTL[D3CD] has to be set to 1 if DAT3 is used as card detection. A pull down is needed as well per spec. It should be an external pull down. MPC8535 HW spec mentions that if SDHC_DAT[3] is not used, SDHC_CD must be used, but it can be implemented by GPIO. What does that mean? Does it mean external (non CPU) GPIO could trigger the SDHC_CD transition? If DAT3 is not used as card detection pin, a separate pin has to be used. For 8535, SDHC_CD_B/GPIO[4] pin is used. PMUXCR[SDHC_CD] pin should set to 1. If PROCTL[D3CD] =0 & PMUXCR[SDHC_CD]=0, the PRSSTAT[CDPL] field is unaffected by the external card detect pin, and will permanently indicate that a card is present.

Please confirm that a PCIe lane on the MPC8308 can be enabled after POR (configured off in h/w but turned on in s/w). If so how this would be implemented? It is possible to control PCIe Lane turned on through s/w. You can control this through SRDSCR2 [0:7]. Through this control you can power -up or power- down individual lanes separately What is the difference between two strap options for PCIe ports - 0b00 or 0b11? In terms of PCIe, options 0b00 and 0b11 are redundant, but in terms of SGMII, they are different 0b00 - 2 lanes are for PCIe; the remaining 2 lanes are powered down 0b11 - 2 lanes are for PCIe; the remaining 2 lanes are for SGMII 0b01 - 3 lanes are for PCIe; the remaining 1 lane is powered down 0b10 - 3 lanes are for PCIe; the remaining 1 lane is for SGMII When SGMII is not used, the corresponding lane(s) should be powered down to save power.

Can you please confirm that the MPC8541 ethernet input clock is actually 2 clocks: one for each eTSEC, with name TSECn_GTX_CLK125/GPIOm? The MPC8541 ballmap spreadsheet only shows one gtx_clk125 pin (like the 8536), but the current data sheet (Revision E) indicates there are two. The ball map shows only primary functions of a pin. By default both the eTSECs would share the same clock i.e TSEC1_GTX_CLK125 @Y29. If required, user can opt to use separate clock for eTSEC2. The separate clock for eTSEC2 is multiplexed with TSEC_1588_TRIG_IN1@AH27 and can be configured using PMUXCR[6:7].

Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8535? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However external ODT is never enabled for SDRAM reads, this could lead to a conclusion that internal ODT is also affected by the TIMING_CFG_5 setting. Can you comment? TIMING_CFG_5 register is only for DRAM ODT (external ODT), this is verified and confirmed. As for your suggestion that because in most cases the read ODT on DRAM is off and hence it has something to do with internal ODT is not a valid assumption. The Read ODT for DRAM is an option available if required. In most cases it will not apply, but there may be a configuration that may require it and then the option is available for such users. Please clarify the meaning of TIMING_CFG_5 register for DDR3 controller of the MPC8535. The sentence ".. relevant ODT signal(s)" is common to all fields. What is this referring to? Is that both a) an internal signal controlling internal IOs (enabled by CFG_2[ODT_CFG]) and b) the external MODT[] signals going to the SDRAM? If yes, what is the delay between the assertion of the internal ODT signal (e.g. set by TIMING_CFG_5[RODT_ON])and actual switching of the internal RTT? These are related to the ODT timings to the DRAM. If ODT during reads is not used, then the RODT_ON and RODT_OFF values can be cleared. These are the ODT signal turn ON/OFF latency. For DDR3 it is defined as WL-2=CWL+AL-2. If one DIMM slot is used then there is no need for dynamic ODT setting.

Can the 8543 support the 16bit FIFO by combining the eTSEC1 pins with the GPIO pins that would otherwise be assigned to eTSEC2 in MPC8548? It is recommended for the unused I/O pins (such as the MECC [0:7]) to be pull down to GND via a 10k resistor. 8543 can, in fact, operate in 16-bit FIFO mode on eTSEC1. The key is to differentiate "signal functionality" from "logic resources." 8543 offers the logic for eTSEC1 and eTSEC3, but all the same signals are still there (including the signals otherwise used for eTSEC2). You'll notice that the references you note (T14-129, T14-173, Section C.2) all clearly make reference to "eTSEC2 signals". According to first bullet in section C.2 - "What signal functionality is NOT included in 8543: - eTSEC2 controller signals. Exceptions to this are when a) the signals are used as GPIO signals, or b) the signals are used to accommodate eTSEC1 in 16-bit FIFO mode." What will the value of GPOUT[0:7] be when they are disabled by GPIOCR? all 0? All 1? or all Hi-Z? GPOUT[0:7] pins are tristated if they are not enabled.