P2020 DDR3 initialization failed

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P2020 DDR3 initialization failed

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kevintse
Contributor I

Hi.

I am writing embedded program for p2020 board and have troubles with configuring ddr controller.

The DDR3 part of the circuit is designed with reference to the P2020RDB-PCA_SPF-2683.PDF. The operating system is linux. When the DDR3 chip capacity is 1G byte (4 pieces MT41K128M16JT-125), the system runs normally. After the capacity is upgraded to 2G byte (4 pieces of MT41K256M16HA-125 or AS4C256M16D3B-12), the system fails to start and DDR3 initialization fails. After DDR3 expansion, what parameters and registers need to be modified to start successfully?

Looking forward to your reply.

#P2020

#DDR3

#initialization

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Bulat
NXP TechSupport
NXP TechSupport

You need to set correct memory bounds (CS0_BNDS) and new number of row bits (CSn_CONFIG) of course. Among timing parameters you need to change tRFC one, for 2Gb devices it should be set to 64 tck (DDR3-800), for 4Gb devices - 104 tck. On the P2020 side tRFC is composed of two registers:TIMING_CFG_1[REFREC] + TIMING_CFG_3[EXT_REFREC].
For 2Gb devices and DDR3-800  following values can be used:
TIMING_CFG_3[EXT_REFREC] = 0x3;
TIMING_CFG_1[REFREC] = 0x8;
For 4Gb devices and DDR3-800  following values can be used:
TIMING_CFG_3[EXT_REFREC] = 0x6;
TIMING_CFG_1[REFREC] = 0x0;

Besides DDR3 setup, you need also to update DDR Local Access Window and MMU window sizes.

Regards,

Bulat