Difference between IRQ0:9 and gpio as an interrupt

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Difference between IRQ0:9 and gpio as an interrupt

Contributor IV

Hi All,

While using GPIO as an interrupt on P2040 chipset i Got a basic doubt regarding interrupts.

1) How IRQ0:9 are different from GPIO as an interrupt ?? In terms of priority, masking etc.

2) How can we decide which interrupt will land on which CPU core ??

Your Help will be highly appreciated.



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NXP TechSupport
NXP TechSupport

1) All GPIO interrupt requests are "ORed" to the single Internal Interrupt 39, so it will be required in the interrupt handler to read GPIO1_GPIER and GPIO2_GPIER to determine specific GPIO signal caused the interrupt.

The interrupt mapping to a a core is performed for External Interrupts in the MPIC_EIDRn (see P2040 RM, 23.3.71 External interrupt n (IRQn) destination register (MPIC_EIDRn)) and for Internal Interrupts - in the MPIC_IIDRn (23.3.74 Internal interrupt n destination register (MPIC_IIDRn)).

2) Because of aforesaid all GPIO interrups can be routed only to a single core by means of the MPIC_IIDR39.

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