The ColdFire chips have a Reset Reason Register. The Power chips (MPC5604 anyway) has a "Functional Event Status Register". Kinetis have "System Reset Status" registers. If the ARM Core doesn't have this internally, this chip doesn't seem to have this available.
> POR, SW_RST or watchdog fail.
The code that performs the SW_RST could leave some "magic values" in SRAM somewhere, as long as there's some SRAM that survives a reset.
I've always tried to have a very high priority software watchdog running slightly ahead of the hardware watchdog. So if the software one triggers you know the hardware one is about to, and the software one can print where the code is stuck or record the stack frame somewhere. You could do the same (have the software one leave some different "magic" in SRAM).
Tom
