Hi there,
before create gerbers for a SGTL5000 based project I'm looking for guidelines for it, in order to minimize noise due to bad ground path, parasitic capacitances, etc.
I'v found none about NXP SGTL5000 Evaluation Platform
can someone help me?
thank you
Hello Federico,
I would like to recommend the following application notes in order to improve your design:
1. AN3962 - PCB Layout Design Guide for Analog Applications.
2. AN4530 - Electrical Connection Recommendations for the Exposed Pad on QFN and DFN Packages.
You may find the KITSGTL5000EVBE as a reference for your design. Please find more information here.
Please let me know if this information is useful for you.
If I misunderstood your question, feel free to let me know. I will be glad to help.
Have a great day.
David Diaz.
PS: If my answer helps to solve your question, please mark it as "Correct". Thank you.