MC50XS4200BEK SO Register reading is not working as per data sheet

[satheeshk]

Hi,

We are using MC50XS4200BEK for load driving. Reading of the register contents is not working as per data sheet. First we write SI STATR register which contains address of the SO register. Then generating 16 clock pulses by sending same word. During second cycle the expected word is the required SO register. But, actually getting the SI STATR register as we write it previously. The observation is whatever the register we write previously is shifting out in the next cycle, irrespective of SI STATR contents.

Thanks

Satheesh Kumar K

[TomasVaverka]

Hi Satheesh,

Do you have a logic analyzer or an oscilloscope to see what is going on the bus? Could you please post it here?

Best regards,

Tomas

[satheeshk]

Hi Tomas,

Thank you for reply.

Here I attached screen shot of SPI bus data captured through logic analyzer.

Channel 0 - MOSI

Channel 1 - RSTB pin, which is always high

Channel 2 - CSB

Channel 3 - MISO

Channel 5 - SCLK

Thanks & Regards

Satheesh

[TomasVaverka]

Hi Satheesh,

From your waveforms, SCLK is idle high. Note that the MC50XS4200 is compatible with SPI Mode 1 which means that the SCLK signal should be idle low,  data are read on the falling edge of clock signal and changed on the rising edge.

Also please make sure that the timing requirements, as shown in Table 5 and Figure 7 of the MC50XS4200 datasheet, are met.

I hope it helps.

Best regards,

Tomas