USBDM wrong speed detection with QE4 and USBDM4.10.5

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USBDM wrong speed detection with QE4 and USBDM4.10.5

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lucianon
Contributor I

Hello PGO,

I create a test project with 9S08QE4 and fbus=8MHz and the TCL interpreter synchronize it with 4.5MHz, the FDIV is 0x16 calculated by initFlash{} script.

It works but the best value for FDIV is 0x2A (200kHZ).

It is very strange because this QE4 when programmed by HCS08_FlashProgrammer seems to be faster than the other families. Do the HCS08_FlashProgrammer use the same sync function of TCL_Interpreter?

I am already ready to make my stand-alone. The TCL_Interpreter are very helpful to understand the flash programming.

thanks,

Luciano Nicolau

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pgo
Senior Contributor V

Hi Luciano,

Sorry I still don't follow what you are saying.

Out of reset I would expect the 9S08QE4 to be operating around 4MHz not 8MHz so the FDIV value calculated is correct.

The value calculated by the 'bean' is for 8 MHz - after the chip is running and the clock has been re-configured.

You can try the following to check:

  • Program your chip with the 'bean' program and confirm that it operates correctly.
  • Using USBDM TCL connect to the chip.
  • Reset into special mode (RESET S S) (corrected)
  • Check the speed - I would expect around 4MHz (8MHz clock)
  • Start your program
  • Check the speed again - it should now be 8MHz (16 MHz clock)
  • Calculate the trim - it should now agree with your value

bye

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lucianon
Contributor I

For HCS08 devices the reset value is always ICSC2 = 01 = Divides selected clock by 2 (default).

It means during reset and synchronizing BDM always get 4.5MHz because it is not started yet.

If the default frequency are always known why we need to guess the FBUS to calculate the FDIV when secured?

Why sometimes the sync command get 8MHz for some HCS devices? It should get 4.5MHz after reset or cycled power because it is not started.

I´m very confused with this.

thank you pgo for answer me.

Luciano

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pgo
Senior Contributor V

Hi Luciano,

After a reset (hardware or software) the device may run in which case who can tell what the clock is as it depends on the program executed,  The CLKSW bit may also be cleared.

After software reset into special mode or POR with BKGD=0 we know the following:

  • The program has not executed so the clock is in reset state
  • The clock trim is initialised to 0x80 which is a 'safe' value
  • The CLKSW bit is set in the BDMSCR register so the BDM clock = bus clock

Some devices may be operating at ~4MHz others ~8MHz.  Depends on the device if I remember correctly some operate at higher frequency out of reset.  The actual frequency will vary from chip-to-chip, even in the same family, due to tolerances in the clock oscillator.

These approximate values are not sufficiently accurate for programming, hence the need to measure (not guess!) the bus frequency using the BDM sync command.

Note: doing a hardware reset does not ensure the above so you will often see different clock values after running a program and then doing a hardware reset.

bye

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pgo
Senior Contributor V

Hi Luciano,

I tried out the scripts with a MC9S08QE8.

Results as follows:

Bus clock from speed command => 4557000

FDIV value calculated by initFlash 4557 =>  0x16 = decimal 22.

Referring to table 4-7 in the MC9S08QE8 reference manual this value looks about right.

Where does your value of 0x2A come from?

bye

PS.  What I should really ask is why you think the actual bus speed is 8MHz which seems to be what you are assuming?

PPS. The programmer may change the clock frequency of the target to obtain higher programming speeds.  The out-of-reset results above may be different to what it uses.

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lucianon
Contributor I

Hi pgo,

If you want to see, attached is my test project with (FBUS=8MHz and FCDIV=0x2A) for CW6.3.

The initialization bean calculate 0x2A as you can see below:

void IFsh1_Init(void)

{

  /* FSTAT: FCBEF=0,FCCF=0,FPVIOL=1,FACCERR=1,??=0,FBLANK=0,??=0,??=0 */

  setReg8(FSTAT, 0x30);                /* Clear FPVIOL & FACERR flag */

  /* FCDIV: DIVLD=0,PRDIV8=0,DIV5=1,DIV4=0,DIV3=1,DIV2=0,DIV1=1,DIV0=0 */

  setReg8(FCDIV, 0x2A);                /* Initialize FCDIV register */

}

This project synchronize as 4.5MHz. I think it is a wrong speed detection because the real speed is 8MHz. It only happen with QE4 or QE8.

But with FCDIV=0x22 it can be program too.

Luciano

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pgo
Senior Contributor V

Hi Luciano,

Sorry I still don't follow what you are saying.

Out of reset I would expect the 9S08QE4 to be operating around 4MHz not 8MHz so the FDIV value calculated is correct.

The value calculated by the 'bean' is for 8 MHz - after the chip is running and the clock has been re-configured.

You can try the following to check:

  • Program your chip with the 'bean' program and confirm that it operates correctly.
  • Using USBDM TCL connect to the chip.
  • Reset into special mode (RESET S S) (corrected)
  • Check the speed - I would expect around 4MHz (8MHz clock)
  • Start your program
  • Check the speed again - it should now be 8MHz (16 MHz clock)
  • Calculate the trim - it should now agree with your value

bye

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