K20 MCG FLL Mode doesn't work.

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

K20 MCG FLL Mode doesn't work.

2,186 Views
markkalior
Contributor II

Can't get K20 MCG FLL Mode to be selected (MCG_S = xxxx11xx instead of MCG_S = xxxx00xx).

 

Details:

1) MQX 4.20:

2) Based on twrk20d72m tower software

     a) tower schematic calls out the PK20DX256VLL7, while the chip used is MK20DX256VMC10.  Had to change the code to support this chip (MK20D10.h instead of MK20D7.h).

     b) RTC crystal is used to drive everything (XTAL32 and EXTAL32, 32.768Khz).   XTAL0 and EXTAL0 are not connected.   The code was changed to support this configuration (Processor Expert           10.4.0).  Attached is the bsp code change for the MCG FLL Mode change.

3) no external FLASH, DDR, or MRAM.

4) IAR IDE and I-Jet debugger (7.40 for ARM).

 

Observed behaviors:

1) IAR IDE and I-Jet debugger seems to work.

2) most K20 register values (debugger) are 0xCDCDCDCD (e.g. MCG_xxx, RCM_xxxx, SIM_xxx).  Clearly this is not correct.  debugger artifact?  K20 problem?  The code does seem to read and       react to these values.   Perhaps this problem is related to Reset signal (see below).   The debugger claims the K20 registers are updated every second.

3) K20 Reset signal (J11) is toggling.  65us period, low for 63us and high for 2us.   WDOG is disabled.  Clock Monitors are disabled.  VDD is 3.3V.  Not using any low power modes.  Removing the      debugger doesn't change this behavior.   Reset net is connected to JTAG (debugger) only, with a 10K pull-up.

4) Can't get K20 FLL Mode to be selected (MCG_S = xxxx11xx instead of MCG_S = xxxx00xx).   Could be the 0xCDCDCDCD problem.

5) The XTAL32 and EXTAL32 pins have no voltages.   I would expect about 1/2 voltage.  I don't think the crystal will oscillate with zero volts.

 

I have checked the layout and schematic to make sure all the VDD and VSS are connected and found no problems.   

Original Attachment has been moved to: K20_bsp.zip

0 Kudos
Reply
4 Replies

1,158 Views
soledad
NXP Employee
NXP Employee

Hello Mark:

  1. The closest MQX BSP to use as clone based for the MK20DX256VMC10 device is the TWR-K60D100M. So, you need to clone the TWR-K60D100M for your board.
  2. It is possible to change the clock configurations.  All MQX BSP's are PE capable and Processor Expert is integrated with CodeWarrior but it is also a standalone tool that can generate code for IAR, Keil, GCC, etc.

        http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PE_DRIVER_SUITE&tid=PEH

        In my opinion it is easier to generate the MCG functions using PE. If you don’t want to use PE you need to modify the bsp_cm.c file. Unfortunately I cannot to provide the exact changes because I don’t have a board in order to test these modifications.

You need to considerate the below information:

  • Check the bsp_cm.c file located at the path: C:\Freescale\Freescale_MQX_4_2\mqx\source\bsp\<name_board>
  • Localize the void _bsp_initialize_hardware(void) function
  • Modify this function according your needs.

C. Less flash memory size is to be modified in the linker command file. The location of the linker file is at

c:\Freescale\Freescale_MQX_4_x\mqx\source\bsp\<platform>\cw\*.lcf.

D. In my opinion the problems with the registers are due to incorrect settings in the BSP.  Please try with these modifications and let me know if this helps.


Have a great day,
Sol

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
Reply

1,158 Views
markkalior
Contributor II

1) I have tried numberous experiments and I can get past the while loops:

  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);

  /* MCG_C4: DMX32=1,DRST_DRS=3 */

  MCG_C4 |= (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03));

  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */

  MCG_C5 = MCG_C5_PRDIV0(0x00);

  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */

  MCG_C6 = MCG_C6_VDIV0(0x00);

  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */

  }

  while((MCG_S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */

  }

2) The code snippet above is from Processor Expert.

3) I have tried numberous experiments and I always have the same problem.   Any know issues with Processor Expert?

4) I have studied the TWR-K60D100M and TWR-K20D72m and both don't have any code for Internal Clocks (FBI, FLL, bsp_cm.c,_xxx_initialize_hardware).

5) bsp_cm.c: _pe_initialize_hardware and _bsp_set_clock_configuration are doing the same thing.   Why are both methods (or functions) called?   Should I set the MCG twice?

6) I tried the AutoTrim, but got stuck in the while loop (why am I not surprised?).

7) any ideas?   

0 Kudos
Reply

1,158 Views
soledad
NXP Employee
NXP Employee

Hello Mark,

Sorry for my delay.

In order to clone a BSP it is very important that you consider the factures and the core frequency; these should be very similar to the custom board. For example, if you want to create a BSP and PSP for a K20dx256z (100MHz) it is necessary to select the BSP and PSP for the TWR-K60D100M because the features and core frequency between both processors (k60 and k20) and the boards are very close.

Please check the attached document (MQX™ RTOS BSP Porting Guide) , in page 11 you can find a tool, use this tool to find the closest MQX BSP to clone based on the Kinetis part number.

With this tool you can verify that the BSP you need to clone is the  TWR-K60D100M.

All the problems that are occurring are due to the clock change you're doing. I am attaching a document (MQX_BSP_Porting_Example_User_Guide.pdf), this document shows an example (page 21), in this example, the BSP needs the clock source changed from a 50 MHz oscillator to an 8 MHz crystal. Also, the example changes the PLL output from 96 MHz to 48 MHz, to force a change to the USB clock dividers, and detail these steps.

Unfortunately I cannot provide an exact example or code, like you need because I don't have a board to test. Sorry for any inconvenience.

Have a nice day!

Sol

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
Reply

1,158 Views
markkalior
Contributor II

A).  I am reluctant to "start over", I have already spent a lot time getting here.   I have been using Processor Expert.  I have attached my code for your review.  "_pe_initialize_hardware()" and "PE_low_level_init()", is where the PE code was inserted. I was hoping you could look at my code and tell me what is wrong.  I am using IAR.

B) I am using PE, see above.

C) I understand, see A)

D) Your response is trival.  I am aware that the code doesn't work, that's why I generated this content.  Telling me I have a mistake in my code isn't helpful.  What would be helpful, is for you to tell me what line of code is wrong.   I taken PE code and insert it into "bsp_cm.c" attached, see A)   ....or maybe I didn't setup PE correctly, you could run PE and see if it matches my PE code.

I am not clear why starting over is quicker than fixing the one or two line of codes that is incorrect.   PE code isn't going to change.   Unless you are telling me twrk20d72m has bugs and its takes too long to debug it.   

0 Kudos
Reply