I am trying to update a project running on a Freescale MK10DN512VLQ10 using MQX 3.7 to use MQX 4.2. I went through the cloning process using twrk60n512 as the base and am running into a lock up situation. In bsp_cm.c, when we go into __pe_initialize_hardware, things seem to be fine until we hit the line setting MCG_C2. Since it's the same processor, why is it setting different values for MCG_C2 and MCG_C1 vs. what it was setting in MQX 3.7?
_bsp_watchdog_disable();
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK40DX256ZVMD10 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* System clock initialization */
/* SIM_SCGC5: PORTA=1 */
SIM_SCGC5 |= (uint32_t)0x0202UL; /* Enable clock gate for ports to enable pin routing */
if ( *((uint8_t*) 0x03FFU) != 0xFFU) {
MCG_C3 = *((uint8_t*) 0x03FFU);
MCG_C4 = (MCG_C4 & 0xE0U) | ((*((uint8_t*) 0x03FEU)) & 0x1FU);
}
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (uint32_t)0x01130000UL; /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 |= (uint32_t)0x00010000UL; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=1 */
SIM_SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/*
** [ENGR288288] Only enable External reference in Low Power Mode
** There is a conflict between VLLSx and GPIO on TWR-K60N512: XTAL and SW1 are using PTA19
** If enable external reference clock (OSCERCLK) and allow it working on STOP mode,
** PTA19 can't be used as input (refer to 10.2.3 section in RM)
*/
#if MQX_ENABLE_LOW_POWER
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (uint8_t)0xA0U;
#else
/* OSC_CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC_CR = (uint8_t)0x00U;
#endif
/* SIM_SOPT2: MCGCLKSEL=0 */
SIM_SOPT2 &= (uint32_t)~0x01UL;
/* MCG_C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=1 */
MCG_C2 = (uint8_t)0x21U;
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (uint8_t)0xA8U;
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=1,PRDIV=0x18 */
MCG_C5 = (uint8_t)0x38U;
/* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=0x18 */
MCG_C6 = (uint8_t)0x18U;
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
