Hardware watchdog

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Hardware watchdog

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bc2
Contributor I

Hi

I am looking to get a hardware watchdog going on a MQX 3.7 MJ51 project. As I understand it the example \ watchdog project is software based.

 

Looking through some of the header files I modiefied bsp_int.c as follows.

 

 // no define for setting cop to 1/4 second
        reg_ptr->SIM.SOPT1 = MCF51XX_SOPT1_STOPE_MASK | MCF51XX_SOPT1_WAITE_MASK | 0x80;
 
      reg_ptr->SIM.SOPT2 = 0;
      /*
       * Add Low voltage detect enable and low voltage detect reset enable
       */
      reg_ptr->PMC.SPMSC1 = MCF51XX_PMC_SPMSC1_LVDE | MCF51XX_PMC_SPMSC1_LVDRE | MCF51XX_PMC_SPMSC1_LVDACK;
   
      reg_ptr->PMC.SPMSC2 = 0;

      /* INTC_WCR: ENB=1,MASK=0 */
      reg_ptr->INTC.WCR = MCF51XX_INTC_WCR_ENB;
     

and added this to one of my tasks

 

      reg_ptr->SIM.SRS = 0x55;
      reg_ptr->SIM.SRS = 0xAA;

 

 

It compiles but I do not have working hardware at home and can not test this. Any one know if this will work, or a better way to do this?

 

Also, anyone know why Freescale does not support the hardware watchdog?

 

thanks

 

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DavidS
NXP Employee
NXP Employee

Hi BC2,

The hardware watchdog is nice for end product but pain in the backside when debugging as often (generically speaking) the hardware watchdog cannot be disable once enabled.

I've implemented it with ColdFire V2 (MCF52259) but not the V1 devices.

I basically did what you did and then had to find various locations in tasks to kick the watchdog to prevent it from activating.

You don't want to place the kicks in the PIT (MQX heart beat and clocking interrupt routine) as tasks could hang and the heart beat continues.  The MCF51JM reference manual has good verbage on this in section 5.3.1 Computer Operating Properly (COP) Watchdog.  Note that the SOPT1/2 register as write once after reset.  So once set you cannot change them dynamically.

Each application is different so the spot to implement the kick is up to the system programmer.  But if others have done this, please let us know what you did to help others.

Hope this helps.

Regards,

David

 

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DavidS
NXP Employee
NXP Employee

Hi BC2,

The hardware watchdog is nice for end product but pain in the backside when debugging as often (generically speaking) the hardware watchdog cannot be disable once enabled.

I've implemented it with ColdFire V2 (MCF52259) but not the V1 devices.

I basically did what you did and then had to find various locations in tasks to kick the watchdog to prevent it from activating.

You don't want to place the kicks in the PIT (MQX heart beat and clocking interrupt routine) as tasks could hang and the heart beat continues.  The MCF51JM reference manual has good verbage on this in section 5.3.1 Computer Operating Properly (COP) Watchdog.  Note that the SOPT1/2 register as write once after reset.  So once set you cannot change them dynamically.

Each application is different so the spot to implement the kick is up to the system programmer.  But if others have done this, please let us know what you did to help others.

Hope this helps.

Regards,

David

 

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